Table 6-3 Dsp Control Register (Dctr) - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
DSP SIDE Programming Model
6.5.1 DSP Control Register (DCTR)
11 10 9
23 22 21
HM2 HM1
* - Reserved, read as zero and should be written with zero.
Bit
0
1
2
3-5
6
13
14
15
16
17
18
19
20-22
23,12-7
The DCTR is a 24-bit read/write control register used by the DSP56300 core to control
the HI32 interrupts, flags, and the host port signal functionality. The DCTR cannot be
accessed by the host processor. All reserved bits are read as zeros and should be
programmed as zeros for future compatibility. The bit manipulation instructions are
useful for accessing individual bits in the DCTR. The DCTR bits are described in the
following paragraphs.
6-12

Table 6-3 DSP Control Register (DCTR)

8 7 6
HINT
20 19 18
HM0 HIRD HIRH
Name
HCIE Host Command Interrupt Enable
STIE Slave Transmit Interrupt Enable
SRIE Slave Receive Interrupt Enable
HF[5:3] Host Flags
HINT Host Interrupt A
HDSM Host Data Strobe Mode
HRWP Host RD/WR Polarity
HTAP Host Transfer Acknowledge Polarity
HDRP Host DMA Request Polarity
HRSP Host Reset Polarity
HIRH Host Interrupt Request Handshake Mode
HIRD Host Interrupt Request Drive Control
HM[2:0] HI32 Mode
reserved
DSP56305 User's Manual
5 4 3
HF5 HF4 HF3
17 16 15
HRSP HDRP HTAP
Function
2 1 0
SRIE STIE HCIE
14 13 12
HRWP HDSM
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