Motorola DSP56305 User Manual page 652

D
bit 15—ESSI Transmit 1 Enable bit (TE1) 7-30
bit 16—ESSI Transmit 0 Enable bit (TE0) 7-31
bit 17—ESSI Receive Enable bit (RE) 7-33
bit 18—ESSI Transmit Interrupt Enable bit
(TIE) 7-34
bit 19—ESSI Receive Interrupt Enable bit
(RIE) 7-34
bit 20—ESSI Transmit Last Slot Interrupt
Enable bit (TLIE) 7-34
bit 21—ESSI Receive Last Slot Interrupt Enable
bit (RLIE) 7-34
bit 22—ESSI Transmit Exception Interrupt
Enable bit (TEIE) 7-35
bit 23—ESSI Receive Exception Interrupt
Enable bit (REIE) 7-35
D
data ALU 1-8
registers 1-8
Data Input bit (DI) 9-15
Data Output bit (DO) 9-15
DE signal 10-4
Debug Event signal (DE signal) 10-4
Debug mode
in OnCE module 10-16
DEBUG_REQUEST instruction 11-11
executing during Stop state 10-17
executing during Wait state 10-17
executing in OnCE module 10-17
DI bit 9-15
DIR bit 9-15
Direct Memory Access (DMA) 1-15
Direction bit (DIR) 9-15
Divide Factor (DF) 1-11
DMA 1-15
triggered by timer 9-29
DO bit 9-15
DO loop 1-10
DRAM 1-13
,
DSP56300 core 1-3 1-6
DSP56300 Family Manual 1-3
DSP56303 Technical Data 1-3
E
ENABLE_ONCE instruction 11-11
Enhanced Synchronous Serial Interface 2-3
2-32
Enhanced Synchronous Serial Interface (ESSI) 1-16
Index-2
,
1-7
, ,
2-29
DSP56305 User's Manual
, , ,
ESSI 2-3 2-4 2-29 2-32
after reset 7-43
asynchronous operating mode 7-50
frame sync length 7-51
frame sync polarity 7-52
frame sync selection 7-51
frame sync word length 7-51
GPIO functionality 7-53
initialization 7-43
interrupts 7-45
Network mode 7-48
Normal mode 7-48
operating mode 7-43
operating modes 7-48
Port Control Register (PCR) 7-54
Port Data Register (PDR) 7-56
Port Direction Register (PRR) 7-55
programming model 7-13
synchronous operating mode 7-50
ESSI Control Register A (CRA) 7-15
ESSI Mode Select bit (MOD) 7-27
ESSI Receive Data Register (RX) 7-40
ESSI Receive Enable bit (RE) 7-33
ESSI Receive Exception Interrupt Enable bit
(REIE) 7-35
ESSI Receive Interrupt Enable bit (RIE) 7-34
ESSI Receive Last Slot Interrupt Enable bit
(RLIE) 7-34
ESSI Receive Shift Register 7-40
ESSI Receive Slot Mask Registers (RSMA,
RSMB) 7-42
ESSI Status Register (SSISR) 7-35
ESSI Time Slot Register (TSR) 7-41
ESSI Transmit 0 Enable bit (TE0) 7-31
ESSI Transmit 1 Enable bit (TE1) 7-30
ESSI Transmit 2 Enable bit (TE2) 7-29
ESSI Transmit Data registers (TX2, TX1, TX0) 7-41
ESSI Transmit Exception Interrupt Enable bit
(TEIE) 7-35
ESSI Transmit Interrupt Enable bit (TIE) 7-34
ESSI Transmit Last Slot Interrupt Enable bit
(TLIE) 7-34
ESSI Transmit Shift Registers 7-40
ESSI Transmit Slot Mask Registers (TSMA,
TSMB) 7-41
ESSI0 (GPIO) 5-3
ESSI1 (GPIO) 5-4
EX bit 10-6
Exit Command bit (EX) 10-6
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