Pci Bus Command (C3-C0) Bits 11-8 - Motorola DSP56305 User Manual

When the DPAR is written by the DSP56300 core, while in the PCI mode (HM=$1),
• MARQ is cleared
• when the HI32 can complete the first data phase (i.e. in a write transaction, the
DSP-to-host data path is not empty; in a read transaction, the host-to-DSP data
path is not full) ownership of the PCI bus is requested and when granted
• the address (from the DPMC and the DPAR) is driven to the HAD31-HAD0
signals and the bus command is driven to the HC3/HBE3-HC0/HBE0 signals
during the PCI address phase.
The DPAR may be written only if MARQ is set.
In memory space accesses, the AR1-AR0 bits have the following meaning:
AR1
0
0
1
The DPAR bits are ignored when not in the PCI mode (HM≠$1).
Hardware and software resets clear A15-A0.
6.5.4.1

PCI Bus Command (C3-C0) Bits 11-8

The C3-C0 define the PCI bus command. PCI bus commands supported by the HI32 as a
PCI master are listed in Table 6-9. When the DPAR is written by the DSP56300 core,
while the HI32 is in the PCI mode (HM=$1), ownership of the PCI bus is requested and,
when granted, the address is driven to the HAD31-HAD0 signals and the bus command
is driven to the HC3/HBE3-HC0/HBE0 signals during the PCI address phase.
MOTOROLA
AR0
0 Linear incrementing
1 PCI Cache line toggle mode (the data must be
arranged by the DSP software)
X Reserved
DSP56305 User's Manual
HOST INTERFACE (HI32)
DSP SIDE Programming Model
Burst Order
6-33