Motorola DSP56305 User Manual page 654

M
Loop Address register (LA) 1-10
Loop Counter register (LC) 1-10
M
MAC 1-9
Manual Conventions 1-5
MBO bit 10-9
MBS0–MBS1 bits 10-12
memory
bootstrap ROM 3-4
enabling breakpoints 10-18
expansion 1-13
external expansion port 1-13
off-chip 1-13
on-chip 1-12
program RAM 3-4
X data RAM 3-5
Y data RAM 3-6
Memory Breakpoint Occurrence bit (MBO) 10-9
Memory Breakpoint Select bits
(MBS0–MBS1) 10-12
memory configuration 3-10
memory spaces 3-10
RAM 3-10
MF bits 4-23
MIPS 1-7
MOD bit 7-27
,
mode control 2-15 2-17
Mode Select bit (MOD) 7-27
modulo adder 1-9
Multiplication Factor bits (MF) 4-23
multiplier-accumulator (MAC) 1-8
O
OBCR register 10-12
bits 0–1—Memory Breakpoint Select bits
(MBS0–MBS1) 10-12
bits 2–3—Breakpoint 0 Read/Write Select bits
(RW00–RW01) 10-12
bits 4–5—Breakpoint 0 Condition Code Select
bits (CC00–CC01) 10-13
bits 6–7—Breakpoint 1 Read/Write Select bits
(RW10–RW11) 10-13
bits 8–9—Breakpoint 1 Condition Code Select
bits (CC10–CC11) 10-14
bits 10–11—Breakpoint 0 and 1 Event Select
bits (BT0–BT1) 10-14
reserved bits—bits 12–15 10-15
Index-4
OCR register
ODEC 10-8
OF0–OF1 bits 7-20
offset adder 1-9
OGDBR register 10-20
OMAC0 comparator 10-11
OMAC1 comparator 10-11
OMAL register 10-11
OMBC counter 10-14
OMLR0 register 10-11
OMLR1 register 10-11
OMR
OMR register 1-11
OnCE 1-4
OnCE Breakpoint Control Register (OBCR) 10-12
OnCE Command Register (OCR) 10-5
OnCE Decoder (ODEC) 10-8
OnCE GDB Register (OGDBR) 10-20
OnCE Memory Address Comparator 0
OnCE Memory Address Comparator 1
OnCE Memory Address Latch register
,
1-9
OnCE Memory Breakpoint Counter (OMBC) 10-14
OnCE Memory Limit Register 0 (OMLR0) 10-11
OnCE Memory Limit Register 1 (OMLR1) 10-11
OnCE module 1-12
OnCE PAB Register for Decode Register
OnCE PAB Register for Execute (OPABEX) 10-21
DSP56305 User's Manual
bits 0–4—Register Select bits (RS0–RS4) 10-6
bit 5—Exit Command bit (EX) 10-6
bit 6—GO Command bit (GO) 10-6
bit 7—Read/Write Command bit (R/W) 10-6
bit 15-Address Tracing Enable bit (ATE) 4-22
,
1-7
commands 10-23
controller 10-5
trace logic 10-15
(OMAC0) 10-11
(OMAC1) 10-11
(OMAL) 10-11
, ,
2-38 10-3
checking for Debug mode 10-24
displaying a specified register 10-26
displaying X data memory 10-27
interaction with JTAG port 10-29
polling the JTAG Instruction Shift
register 10-24
reading the Trace buffer 10-25
returning to Normal mode 10-28
saving pipeline information 10-25
(OPABDR) 10-20
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