Motorola DSP56305 User Manual page 252

Table 6-18 Host Port Signals - Detailed Description (Sheet 12 of 13)
HI32
Port
a
Pin
HP48-HP41
HRST
Hardware Reset
Input signal.
Forces the HI32 PCI sequencer to the
initial state. All signals are forced to
the disconnected state.
HRST is asynchronous to HCLK.
PCI
HD23-HD16
Data Bus
Tri-state, bidirectional bus.
Used to transfer data between the host processor and the
HI32.
This bus is released (disconnected) when the HI32 is not
selected by HA10-HA0. The HD23-HD16 signals are
driven by the HI32 during a read access, and are inputs to
the HI32 during a write access.
HD23-HD16 outputs are high impedance if HRF≠$
HD23-HD16 inputs are disconnected if HTF≠$
When operating with a host bus less than 24 bits wide, the
data signals that are not used for transferring data must be
forced or pulled to Vc
operating with a 16-bit bus (e.g. ISA bus), HP48-HP41
must be forced or pulled up to Vcc or pulled down to
GND.
NOTE: It is recommended to force or pull these unused
data lines to GND, as forcing or pulling these lines to Vcc
will set the corresponding bits in the HCTR, when the
external host writes to this register.
HRST
Hardware Reset
Schmitt trigger input signal.
Forces the HI32 to its initial state. All signals are forced to the
disconnected state.
The polarity of the HRST signal is controlled by HRSP bit in the DCTR.
HI32 Mode
Enhanced Universal
. For example: when
c or to GND
b
Universal
GPIO
Disconnected
0
.
0
.