Motorola DSP56305 User Manual page 214

24-bit digital signal processor
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HOST INTERFACE (HI32)
HOST SIDE Programming Model
HRF
HRF
1
0
0
1
The three least significant HRXS bytes are
output right aligned and zero extended.
HI32
$0
$0
1
0
The three least significant HRXS bytes are
output right aligned and sign extended.
HI32
1
1
The three least significant HRXS bytes are
output left aligned and zero filled.
HI32
6-66
Table 6-16 Receive Data Transfer Format
DSP to Host Data Transfer Format
PCI mode
GDB/MDDB
DTXS
HRXS
HDTFC
PCI bus
GDB/MDDB
DTXS
HRXS
HDTFC
S
PCI bus
S
GDB/MDDB
DTXS
HRXS
HDTFC
$0
PCI bus
$0
DSP56305 User's Manual
Universal Bus mode
The two least significant HRXS bytes
are output to HD15-HD0.
X
HI32
X
X
The two least significant HRXS bytes
are output to HD15-HD0.
X
HI32
X
X
The two middle HRXS bytes are output
to HD15-HD0.
X
HI32
X
X
GDB/MDDB
DTXS
HRXS
HDTFC
Host bus
GDB/MDDB
DTXS
HRXS
HDTFC
Host bus
GDB/MDDB
DTXS
HRXS
HDTFC
Host bus
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