Received Master Abort (Rma) Bit 29; Signaled System Error (Sse) Bit 30; Detected Parity Error (Dpe) Bit 31; Cstr Reserved Bits 23-16 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
6.6.8.11

Received Master Abort (RMA) Bit 29

The RMA indicates a master-abort PCI bus state has been generated. When in the PCI
mode (HM=$1) and the HI32, as a master device, terminates its transaction with
master-abort, the RMA is set. The RMA bit is cleared when it is written with one by the
host processor.
The personal hardware reset clears RMA.
6.6.8.12

Signaled System Error (SSE) Bit 30

The SSE indicates a system error has occurred. When in the PCI mode (HM=$1) and the
HI32 asserts HSERR signal, the SSE is set. The SSE bit is cleared when it is written with
one by the host processor.
The personal hardware reset clears SSE.
6.6.8.13

Detected Parity Error (DPE) Bit 31

The DPE indicates a parity error has been detected by the HI32 hardware. When in the
PCI mode (HM=$1) and the HI32 detects either address or data parity error, the DPE is
set. The DPE bit is cleared when it is written with one by the host processor.
The personal hardware reset clears DPE.
6.6.8.14

CSTR Reserved Bits 23-16

These unused bits are reserved for future PCI expansion and read by the host processor
as zeros.
6.6.8.15

CCMR Reserved Bits 15-10

These bits are reserved for future PCI expansion and should be written with zeros for
upward compatibility. They are read by the host processor as zeros.
6.6.8.16

CCMR Not Implemented Bits 9, 5-3

These not implemented bits are reserved for future expansion and should be written
with zeros for upward compatibility. They are read by the host processor as zeros.
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