Figure 6-2 Host Side Registers (Pci Memory Address Space); Figure 6-3 Host Side Registers (Pci Configuration Address Space) - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
Figure 6-2 Host Side Registers (PCI Memory Address Space
Base Address: $0000
Base Address: $000C
Base Address: $0010
Base Address: $0014
Base Address: $0018
Base Address: $001C
Base Address: $FFFC
Figure 6-3 Host Side Registers (PCI Configuration Address Space
$00(CDID/CVID)
$04(CSTR/CCMR)
$08(CCCR/CRID)
$0C(CLAT)
$10(CBMA)
$14
$F8
$FC(CILP)
1. Addresses shown are in bytes. The base address is defined by the CBMA register
2. Addresses shown are in bytes.
6-52
Reserved (4 Dwords)
HI32 Control Register (HCTR)
HI32 Status Register (HSTR)
Host Command Vector Register (HCVR)
Host Transmit/Slave Receive Data Register (HTXR/HRXS)(16377 Dwords)
Device ID (CDID)
Status (CSTR)
Class Code (CCCR)
Header Type (CHTY) Latency Timer (CLAT)
Memory Space Base Address (CBMA)
Reserved(58 Dwords)
MAX_LAT MIN_GNT
DSP56305 User's Manual
1
)
Vendor ID (CVID)
Command (CCMR)
Revision ID (CRID)
Interrupt Line Interrupt Signal
MOTOROLA
2
)