Memory Space (Ms1-Ms0) Bits 2 And 1; Pre-Fetch (Pf) Bit 3; Memory Base Address (Pm31-Pm16) Bits 31-4; Bits 23-16 - Motorola DSP56305 User Manual

6.6.11.2

Memory Space (MS1-MS0) Bits 2 and 1

The MS1 and MS0 bits encode that CBMA register is 32 bits wide and mapping can be
done anywhere in the 32 bit memory space. The MS1 and MS0 are hardwired to zeros
and is not affected by any type of reset.
6.6.11.3

Pre-fetch (PF) Bit 3

The PF bit indicates that the data is pre-fetchable or not. PF is hardwired to zero and is
not affected by any type of reset.
6.6.11.4

Memory Base Address (PM31-PM16) Bits 31-4

The PM31-PM4 bits define the HI32 base address when it is mapped into the PCI
memory space. The PM15-PM4 are hardwired to zero, while PM31-PM16 can be written
by the PCI master during system configuration.
The HI32 target occupies 16384 Dwords of the PCI memory space. The HI32 is selected
by the 20 most significant PCI address signals HAD31-HAD12, and the twelve least
significant address signals HAD11-HAD0 are used to select the HI32 registers on the
host side (see Figure 6-2).
The personal hardware reset clears PM31-PM16.
6.6.11.5 Universal Bus Mode Base Address (GB10-GB3) Bits 23-16
The GB10-GB3 bits define the HI32 base address when it is mapped into the Universal
Bus mode space. The remaining CBMA bits are ignored in Universal Bus modes.
The HI32 slave occupies eight locations in the Universal Bus mode space. The HI32 is
selected by the eight most significant address signals HA10-HA3, and the three least
significant address signals HA2-HA0 are used to select the HI32 registers on the host
side.
All reserved register addresses are read as zeros and should be written with zeros for
upward compatibility (see Figure 6-4).
The personal hardware reset clears GB10-GB3.
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
HOST SIDE Programming Model
6-87