Motorola DSP56305 User Manual page 625

24-bit digital signal processor
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Application:
HOST (HI08)
Receive Request Enable
DMA Off
DMA On
Transmit Request Enable
DMA Off
DMA On
HDRQ HREQ/HTRQ HACK/HRRQ
0
HREQ
1
HTRQ
Host Flags
Write Only
Host Little Endian
Initialize (Write Only)
0 = ÷ No Action
Receive Data Register Full
0 = Wait
Transmit Data Register Empty
0 = Wait
Transmitter Ready
0 = Data in HI
Host Flags
Read Only
DMA Status
0 = ÷ DMA Disabled
Host Request
0 = ÷ HREQ Deasserted 1 = ÷ HREQ Asserted
Figure D-9 Interrupt Control and Interrupt Status Registers
MOTOROLA
Processor Side
0 = ÷ Interrupts Disabled
1 = Interrupts Enabled
0 = Host → DSP
1 = DSP → Host
0 = ∏ Interrupts Disabled
1 = Interrupts Enabled
0 = DSP → Host
1 = Host → DSP
HACK
HRRQ
1 = ÷ Initialize DMA
Interrupt Control Register (ICR)
1 = Read
1 = Write
1 = Data Not in HI
1 = ÷ DMA Enabled
Interrupt Status Register (ISR)
$2 Read/Write
DSP56305 User's Manual
PROGRAMMING REFERENCE
7
6
5
INIT
*
HLEND
0
X:$
Read/Write
Reset = $0
7
6
5
*
HREQ
DMA
0
Reset = $06
= Reserved, Program as 0
*
Date:
Programmer:
Sheet 4 of 6
4
3
2
1
0
HF1
HF0
HDRQ
TREQ
RREQ
4
3
2
1
0
HF3
HF2
TRDY
TXDE
RXDF
D-25

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