Essi Transmit Interrupt Enable (Tie) Crb Bit 18; Essi Receive Interrupt Enable (Rie) Crb Bit 19 - Motorola DSP56305 User Manual

7.4.2.18

ESSI Transmit Interrupt Enable (TIE) CRB Bit 18

Setting the TIE bit enables a DSP transmit interrupt, which is generated when both the
TIE and the TDE bits in the ESSI Status Register are set. When TIE is cleared, the transmit
interrupt is disabled. The use of the transmit interrupt is described in Section 7.5.2.
Writing data to the data registers of the enabled transmitters or to the TSR clears TDE
and also clears the interrupt. Transmit interrupts with exception conditions have higher
priority than normal transmit data interrupts. If the Transmit Underrun Run (TUE) bit is
set, signaling that an exception has occurred, and the TEIE bit is set, the ESSI requests an
SSI transmit data with exception interrupt from the interrupt controller.
TIE is cleared by either a hardware reset signal or a software reset instruction.
7.4.2.19

ESSI Receive Interrupt Enable (RIE) CRB Bit 19

Setting the RIE enables a DSP receive data interrupt, which is generated when both the
RIE and Receive Data Register Full (RDF) bit (in the SSISR) are set. When RIE is cleared,
this interrupt is disabled. The use of the receive interrupt is described in Section 7.5.2.
Reading the Receive Data Register clears RDF and the pending interrupt. Receive
interrupts with exception have higher priority than normal receive data interrupts. If the
Receiver Overrun Error (ROE) bit is set, signaling that an exception has occurred, and
the REIE bit is set, the ESSI requests an SSI receive data with exception interrupt from
the interrupt controller.
RIE is cleared by either a hardware reset signal or a software reset instruction.
7.4.2.20 ESSI Transmit Last Slot Interrupt Enable (TLIE) CRB Bit 20
Setting the TLIE bit enables an interrupt at the beginning of the last slot of a frame when
the ESSI is in Network mode. When TLIE is set, the DSP is interrupted at the start of the
last slot in a frame regardless of the Transmit Mask Register setting. When TLIE is
cleared, the transmit last slot interrupt is disabled. The use of the transmit last slot
interrupt is described in Section 7.5.2.
TLIE is cleared by either a hardware reset signal or a software reset instruction. TLIE is
disabled when the ESSI is in On-demand mode (DC [4:0]= 00000, in CRA Bits 16-12).
7.4.2.21 ESSI Receive Last Slot Interrupt Enable (RLIE) CRB Bit 21
Setting the RLIE bit enables an interrupt after the last slot of a frame ends when the ESSI
is in Network mode. When RLIE is set, the DSP is interrupted after the last slot in a
frame ends regardless of the Receive Mask Register setting. When RLIE is cleared, the
receive last slot interrupt is disabled. The use of the receive last slot interrupt is
described in Section 7.5.2.
RLIE is cleared by either a hardware reset signal or a software reset instruction. RLIE is
disabled when the ESSI is in On-demand mode (DC [4:0]= 00000, in CRA Bits 16-12).
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Enhanced Synchronous Serial Interface (ESSI)
DSP56305 User's Manual
ESSI Programming Model
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