Essi Status Register (Ssisr); Serial Input Flag 0 (If0) Ssisr Bit 0 - Motorola DSP56305 User Manual

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
7.4.2.22 ESSI Transmit Exception Interrupt Enable (TEIE) CRB Bit 22
When the TEIE bit is set, the DSP is interrupted when both TDE and TUE in the ESSI
Status Register are set. When TEIE is cleared, this interrupt is disabled. The use of the
transmit interrupt is described in Section 7.5.2. Reading the Status Register followed by
writing to all the data registers of the enabled transmitters clears both TUE and the
pending interrupt.
TEIE is cleared by either a hardware reset signal or a software reset instruction.
7.4.2.23 ESSI Receive Exception Interrupt Enable (REIE) CRB Bit 23
When the REIE bit is set, the DSP is interrupted when both RDF and ROE in the ESSI
Status Register are set. When REIE is cleared, this interrupt is disabled. The use of the
receive interrupt is described in Section 7.5.2. Reading the Status Register followed by
reading the Receive Data Register clears both ROE and the pending interrupt.
REIE is cleared by either a hardware reset signal or a software reset instruction.
7.4.3

ESSI Status Register (SSISR)

The SSISR (see Figure 7-8 on page 7-13) is a 24-bit read-only Status Register used by the
DSP to read the status and serial input flags of the ESSI. The meaning of the SSISR bits is
described in the following paragraphs. When the SSISR is read to the internal data bus,
the register contents occupy the low-order byte of the data bus and the remaining bus
bits are read as zeros.
7.4.3.1

Serial Input Flag 0 (IF0) SSISR Bit 0

The IF0 bit is enabled only when SC0 is an input flag and the Synchronous mode is
selected (i.e., when SC0 is programmed as ESSI in the Port Control Register (PCR), the
SYN bit is set, and the TE1 and SCD0 bits are cleared). See Figure 7-3.
The ESSI latches data present on the SC0 signal during reception of the first received bit
after the frame sync is detected. The IF0 bit is updated with this data when the data in
the Receive Shift Register is transferred into the Receive Data Register.
If it is not enabled, the IF0 bit is cleared.
Hardware, software, ESSI individual, and stop reset clear the IF0 bit.
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