Header Type (Ht7-Ht0) Bits 23-16 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
6.6.10 Header Type/Latency Timer Configuration Register
(CHTY/CLAT)
31 30 29 28
15 14 13 12
LT7 LT6 LT5 LT4
Not implemented, read as zero and should be written zero
Bit
CLAT
CHTY 23-16
31-24
The CHTY/CLAT is a PCI standard 32-bit read/write register mapped into the PCI
configuration space, when in the PCI mode or in mode 0 (HM=$1 or $0). The
CHTY/CLAT is accessed if a configuration read/write command is in progress and the
PCI address is $0C. In the Self Configuration mode (HM = $5): the DSP56300 core can
indirectly access the CLAT (Section 6.7).
The CHTY/CLAT is written in accordance with the byte enables. Byte lanes that are not
enabled are not written and the corresponding bits remain unchanged.
The CHTY/CLAT cannot be accessed by the host when not in the PCI mode (HM≠$1).
The CHTY/CLAT bits are described in the following paragraphs.
6.6.10.1

Header Type (HT7-HT0) Bits 23-16

The read-only bits HT7-HT0 identify the layout of bytes $10-$3F in the configuration
space and also whether or not the device contains multiple functions. This byte is
hardwired to the value $00.
6-84
27 26 25
11 10 9
LT3 LT2 LT1
Name
7-0 not implemented
15-8 LT7-LT0
HT7-HT0
not implemented
DSP56305 User's Manual
24 23 22 21
HT7 HT6 HT5
8 7 6 5
LT0
Latency Timer (High)
Header Type (hardwired to $00)
20 19 18 17
HT4 HT3 HT2 HT1
4 3 2 1
Function
MOTOROLA
16
HT0
0