Emi Operation During Stop - Motorola DSP56009 User Manual

Example 4-5 Block Transfer from Internal to External Memory
The following procedure performs a block-data transfer of N words (N>1) from
internal DSP memory to external memory, without checking status flags or using
interrupts. Using this method, it is necessary to know how much time is taken by
each memory access. For this particular example, it is assumed that the EMI is
accessing an external SRAM with zero wait states, transferring 24-bit words over
an 8-bit bus, resulting in 12 clock cycles (6 instruction cycles) per word transfer.
wr_transfer
move #w_buff,r7
movep #w_off,x:EWOR
movep #w_base,x:EBAR0
movep #RAM,x:ECSR
movep y:(r7)+,x:EDWR0
do #(N–1),end_w
movep y:(r7)+,x:EDWR0
rep #2
nop
end_w
4.5.4

EMI Operation During Stop

The EMI operation cannot continue when the DSP is in the Stop state, since no DSP
clocks are active. Note that DRAM refresh cycles are suspended, effectively causing
the loss of data in the DRAMs. While the DSP is in the Stop state, the EMI will remain
in the individual reset state and the status bits in ECSR will be cleared. No control
bits in the ECSR and ERCRs are affected.
4.5.5 EMI Operation During Wait
The EMI will continue operating even if the DSP is in the Wait state. Ongoing and
pending EMI accesses will complete normally. Then, the EMI will remain in the Idle
state until more read- or write-access triggers arrive from the DSP core, after the
device exits the Wait state. No control or status bits in the ECSR and ERCR are
affected by the Wait state.
MOTOROLA
; pointer to internal memory
; write offset
; write base address
; EINW = 1
; first write
; N>1
; initiate next write
; wait 8 clock cycles
; (4 inst cycles)
; or do something useful
DSP56009 User's Manual
External Memory Interface
EMI Operating Considerations
4-45