Table 4-17 Typical Dram Refresh Timing Requirements - Motorola DSP56009 User Manual

4.4.5 DRAM Refresh Timing
Table 4-17 shows the typical refresh requirements of some Motorola DRAM devices.
Note that the column "periodic refresh per row" refers to the time between the
refresh cycles if refreshing is continuous.

Table 4-17 Typical DRAM Refresh Timing Requirements

Device
MCM514256A
MCM51L4256A
MCM514400
MCM51L4400
MCM84000
MCM8L4000
To program the refresh timer for periodic refresh requests, the following equation can
be used:
where:
• ECD is the refresh divider value, an integer in the range of 1 to 256.
• PRF is the DRAM periodic refresh period (in seconds) per row (see
Table 4-17).
• FREQ is the internal device operating frequency in Hz.
• EPS is the prescaler value: 1, 8, or 64.
If the refresh cycles are to be executed in a single burst, it is possible to program the
refresh timer for the highest refresh request rate possible.
Table 4-18 shows the timings and bit settings for continuous refresh cycles, cross
referenced with appropriate clock frequencies.
Note: For the continuous method, the DRAMs require a certain time between the
refresh of each row. This time does not change for DRAMs of different sizes.
MOTOROLA
Number of
Size
rows
256 K × 4
512
256 K × 4
512
1 M × 4
1024
1 M × 4
1024
4 M × 8
1024
4 M × 8
1024
PRF FREQ
≤
ECD --------------------------------- -
EPS
DSP56009 User's Manual
External Memory Interface
Whole refresh
cycle
8 ms
64 ms
16 ms
128 ms
16 ms
128 ms
×
DRAM Refresh
Periodic
refresh per
row
15.6 µs
124.8 µs
15.6 µs
124.8 µs
15.6 µs
124.8 µs
4-35