Program Overlay; Single Delay Line - Motorola DSP56009 User Manual

C.4

PROGRAM OVERLAY

The following routine illustrates a program overlay by replacing N instruction words
in the internal program memory. The EMI operates in the linear SRAM mode (EAM
(3:0) = 0) with 0 wait states. It is also assumed that the external memory device
(EPROM/SRAM) receives its chip select from GPIO3.
overlay
movep #OL_SRAM,x:ECSR
movep $000f07x,x:GPIOR
movep #>EXT_PROG_BUF,x:EBAR0
movep #0,x:EOR0
move #>INT_PROG_BUF,r0
movep #0,x: EOR0
bset #ERTS,x:ECSR
do #(N-2),end_OL
rep #1
nop
movep x:EDRR0,p:(r0)+
end_OL
bclr #ERTS,x:ECSR
movep x:EDRR0,p:(r0)+
movep x: EDRR0,p:(r0)+
bset #GPIOR,x:GPIOR
C.5

SINGLE DELAY LINE

The following routine is an example of a single delay line, as illustrated in
Figure C-3 . This type of routine is typically used in surround sound or reverb
applications.
Delay_Line
movep #RAM,x:ECSR
movep y:Write_Off,x:EWOR
movep y:Delay Base,x:EBAR0
movep #(T_dly-1),x:EOR0
movep x:SAMPLE,x:EDWR0
movep x:EBAR0,y:Delay_Base
nop
movep x:EDRR0,y0
MOTOROLA
; RAM definition
; assert GPIO3 - enable CS
; start address of external buffer
; drive 1st read trigger
; start address of internal buffer
; drive 2nd read trigger
; set read triggers by reading EDDR
; loop to drive more (N-2) triggers
; move previous read data to PMEM and
; trigger next read cycle
; turn off read triggers by EDRR read
; move instruction #N-1 to PMEM
; move instruction #N to PMEM
; negate GPIO3 - disable CS
; use EINR = 1.
; optional change of write offset
; load base address
; read trigger for delayed sample
; write trigger for current sample
; store updated base address
; nop or other
; read the delayed data
DSP56009 User's Manual
Application Examples
C-5