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Overview
DSP56009 Architectural Overview
1.3.1
Memory and Peripheral Modules
The following memory and peripheral modules are included on the DSP56009:
• External Memory Interface (EMI)—The EMI provides simple connection to
external DRAM and/or SRAM and/or EPROM memories. This memory
interface is designed to provide a simple and inexpensive connection to large
DRAM memories (up to two 4 M
configurable as either 4 or 8 bits wide, providing a convenient interface to
standard DRAM, EPROM, and SRAM parts. Data word packing/unpacking is
automatic to simplify and accelerate converting between memory word size
and data word size. Absolute addressing can be used for random memory
access, program bootstrap, overlays, and to access external peripherals.
Relative addressing, assisted by base-offset registers, can easily be used to set
up delay lines.
• Serial Host Interface (SHI)—The SHI provides a fast, yet simple serial
interface to connect the DSP56009 to a host processor or to another serial
peripheral device. Two serial protocols are available: the Motorola Serial
Peripheral Interface (SPI) bus and the Philips Inter Integrated-circuit Control
2
(I
C) bus. The SHI will operate with 8-, 16-, and 24-bit words and the receiver
has an optimal 10-word FIFO register to reduce the receive interrupt rate.
• Serial Audio Interface (SAI)—The SAI provides a synchronous serial
interface that allows the DSP56009 to communicate using a wide range of
standard serial data formats used by audio manufacturers at bit rates up to
one-third the DSP core clock rate (e.g., 27 MHz for a 81 MHz clock). There are
three synchronized data transmission lines and two synchronized data
reception lines, all of which are double-buffered.
• General Purpose Input/Output (GPIO)—The GPIO has four dedicated
signals that can be independently programmed to be inputs, standard TTL
outputs, open collector outputs, or disconnected.
1.3.2
DSP Core Processor
The 24-bit DSP56000 core is composed of a Data ALU, an AGU, a Program Controller
(PC), and the buses that connect them together. The OnCE port and a PLL are
integral parts of this processor. Figure 1-1 on page 1-9 illustrates the DSP block
diagram, showing the components of the core processor, as well as the peripherals
specific to the DSP56009. The following paragraphs present a brief overview of the
DSP56000 core processor. For more thorough detail, refer to the DSP56000 Family
Manual.
1-10
×
4 bits) for audio delay lines. The port is
DSP56009 User's Manual
MOTOROLA
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