Figure 4-10 Dram For Data Delay Buffers And For Sram For Bootstrap; Emi-To-Memory Connection - Motorola DSP56009 User Manual

External Memory Interface

EMI-to-Memory Connection

4.7 EMI-TO-MEMORY CONNECTION
The EMI can be easily interfaced directly to both SRAM and DRAM devices via its
external pins. No interface logic is required. Usually the hardware designer will
connect DRAM or SRAM to the EMI to implement data buffers that will be accessed
using the Relative Addressing modes. It is possible to concurrently connect an
additional static memory device if one of the GPIO pins or another external source is
used as device select for the device and if the device is accessed using the Absolute
Addressing mode. The Absolute Addressing mode is useful for program bootstrap or
overlays.
Figure 4-10 shows how to connect two 256 K × 4 DRAM devices for the data buffers
and an SRAM for program bootstrap or overlays.
MA[14:0]
MD[7:0]
DSP
(EMI)
MRAS
MCAS

Figure 4-10 DRAM for Data Delay Buffers and for SRAM for Bootstrap

4-48
GPIO3
MWR
MRD
DSP56009 User's Manual
A[14:0]
DQ[7:0]
SRAM
(MCM60256A)
E
W
G
A[8:0]
A[8:0]
DQ[3:0]
DQ[3:0]
DRAM
MCM514256A
MCM514256A
W
W
G
G
RAS
RAS
CAS
CAS
Absolute
Addressing
DRAM
Relative
Addressing
DRAM
AA0260k
MOTOROLA