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Signal Descriptions
Serial Host Interface (SHI)
2.7
SERIAL HOST INTERFACE (SHI)
The Serial Host Interface (SHI) has five I/O signals, which may be configured to
operate in either SPI or I
Signal
Signal Name
Type
SCK
Input or
Output
SCL
Input or
Output
2-14
2
C mode. Table 2-8 lists the SHI signals.
Table 2-8 Serial Host Interface (SHI) signals
State
during
Reset
Tri-stated
SPI Serial Clock (SCK)—The SCK signal is an
output when the SPI is configured as a master, and
a Schmitt-trigger input when the SPI is configured
as a slave. When the SPI is configured as a master,
the SCK signal is derived from the internal SHI
clock generator. When the SPI is configured as a
slave, the SCK signal is an input, and the clock
signal from the external master synchronizes the
data transfer. The SCK signal is ignored by the SPI
if it is defined as a slave and the Slave Select (SS)
signal is not asserted. In both the master and slave
SPI devices, data is shifted on one edge of the SCK
signal and is sampled on the opposite edge where
data is stable. Edge polarity is determined by the
SPI transfer protocol.
2
I
bus transactions in the I
Schmitt-trigger input when configured as a slave,
and an open-drain output when configured as a
master. SCL should be connected to V
pull-up resistor. The maximum allowed internally
generated bit clock frequency is
mode and
clock on EXTAL. The maximum allowed
externally generated bit clock frequency is
for the SPI mode and
signal is tri-stated during hardware reset, software
reset, or individual reset (no need for external
pull-up in this state).
DSP56009 User's Manual
Signal Description
C Serial Clock (SCL)—SCL carries the clock for
Fosc
/
for the I
6
Fosc
2
C mode. SCL is a
through a
CC
Fosc
/
for the SPI
4
2
C mode where F
osc
Fosc
2
/
for the I
C mode. This
5
MOTOROLA
is the
/
3
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