Table of Contents
Advertisement
Overview
DSP56009 Architectural Overview
– Up to 2304 × 24-Bit from X and Y data RAM can be switched to Program
RAM for a total of 2816 × 24-bit Program RAM
• Peripheral modules:
– External Memory Interface (EMI), implemented as a peripheral,
supporting:
• Direct connection of page-mode DRAMs: 64 K × 4 bits, 64 K × 8 bits, 256
K × 4 bits, 256 K × 8 bits, 1 M × 4 bits, 1 M × 8 bits, 4 M × 4 bits, and 4 M
× 8 bits
• SRAMs (one to four): 256 K × 8 bits
• Bootstrap from EPROM
• Data bus may be 4 or 8 bits wide
• Data words may be 8, 12, 16, 20, or 24 bits wide
– Serial Host Interface (SHI): SPI and I
10-word receive FIFO register, support for 8-, 16-, and 24-bit words
– Serial Audio Interface (SAI) includes two receivers and three transmitters,
master or slave capability, and implementation of Philips, Sony, and
Matsushita audio protocols; two complete sets of SAI interrupt vectors
– Four independent, programmable GPIO lines
1.3
DSP56009 ARCHITECTURAL OVERVIEW
The DSP56009 is a member of the 24-bit DSP56000 family. The DSP is composed of
the 24-bit DSP56000 core, memory, and a set of peripheral modules as shown in
Figure 1-1 on page 1-9. The 24-bit DSP56000 core is composed of a Data ALU, an
Address Generation Unit (AGU), a Program Controller, an On-Chip Emulation
(OnCE) port, and a PLL designed to allow the DSP to run at full speed while using a
low-speed clock. The DSP56000-family architecture, upon which the DSP56009 is
built, was designed to maximize throughput in data-intensive digital signal
processing applications. The result is a dual-natured, expandable architecture with
sophisticated on-chip peripherals and versatile GPIO.
1-8
2
DSP56009 User's Manual
C protocols, single master capability,
MOTOROLA
Advertisement
Table of Contents
