Table 2-5 External Memory Interface (Emi) Signals - Motorola DSP56009 User Manual

Table 2-4 Clock and PLL Signals (Continued)
Signal Signal
Name Type
PCAP Input
PINIT Input
2.5 EXTERNAL MEMORY INTERFACE (EMI)

Table 2-5 External Memory Interface (EMI) Signals

Signal
Signal Name
MA0–MA14 Output
MOTOROLA
State
during
Reset
Input PLL Filter Capacitor—This input is used to connect a
high-quality (high "Q" factor) external capacitor needed
for the PLL filter. The capacitor should be as close as
possible to the DSP with heavy, short traces connecting
one terminal of the capacitor to PCAP and the other
terminal to V
specified in the DSP56009 Technical Data sheets.
When short lock time is critical, low dielectric absorption
capacitors such as polystyrene, polypropylene, or teflon
are recommended.
If the PLL is not used (i.e., it remains disabled at all
times), there is no need to connect a capacitor to the
PCAP pin. It may remain unconnected, or be tied to
either V
cc
Input PLL Initialization (PINIT)—During the assertion of
hardware reset, the value on the PINIT line is written into
the PEN bit of the PCTL register. When set, the PEN bit
enables the PLL by causing it to derive the internal clocks
from the PLL voltage controlled oscillator output. When
the bit is cleared, the PLL is disabled and the DSP's
internal clocks are derived from the clock connected to
the EXTAL signal. After hardware RESET is deasserted,
the PINIT signal is ignored.
State
during
Type
Reset
Table 2-6
DSP56009 User's Manual
External Memory Interface (EMI)
Signal Description
. The required capacitor value is
CCP
or GND.
Signal Description
Memory Address Lines 0–14—MA0–MA10
provide the multiplexed row/column
addresses for DRAM accesses and MA0–MA14
provide the non-multiplexed address lines 0–14
for SRAM accesses.
Signal Descriptions
2-7