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External Memory Expansion Port (Port A)
2.5
External Memory Expansion Port (Port A)
Note:
When the DSP56303 enters a low-power standby mode (Stop or Wait), it releases
bus mastership and tri-states the relevant Port A signals: A[0–17], D[0–23],
AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK.
2.5.1
External Address Bus
Signal
Type
Name
A[0–17]
Output
2.5.2
External Data Bus
Signal
Type
Name
D[0–23]
Input/Output
2.5.3
External Bus Control
Signal
Type
Name
AA0/RAS0–
Output
Tri-stated
AA3/RAS3
RD
Output
Tri-stated
WR
Output
Tri-stated
2-6
Table 2-6. External Address Bus Signals
State During Reset,
Stop, or Wait
Tri-stated
Table 2-7. External Data Bus Signals
State During Reset,
Stop, or Wait
Tri-stated
Table 2-8. External Bus Control Signals
State During Reset,
Stop, or Wait
Address Attribute or Row Address Strobe—As AA, these signals
function as chip selects or additional address lines. Unlike address
lines, however, the AA lines do not hold their state after a read or write
operation. As RAS, these signals can be used for Dynamic Random
Access Memory (DRAM) interface. These signals have programmable
polarity.
Read Enable—When the DSP is the bus master, RD is asserted to
read external memory on the data bus (D[0–23]). Otherwise, RD is
tri-stated.
Write Enable—When the DSP is the bus master, WR is asserted to
write external memory on the data bus (D[0–23]). Otherwise, WR is
tri-stated.
DSP56303 User's Manual
Signal Description
Address Bus—When the DSP is the bus master, A[0–17] specify
the address for external program and data memory accesses.
Otherwise, the signals are tri-stated. To minimize power
dissipation, A[0–17] do not change state when external memory
spaces are not being accessed.
Signal Description
Data Bus—When the DSP is the bus master, D[0–23] provide the
bidirectional data bus for external program and data memory
accesses. Otherwise, D[0–23] are tri-stated.
Signal Description
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