B-21 Timer Control/Status Register (Tcsr) - Motorola DSP56303 User Manual

24-bit digital signal processor
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Programming Sheets
Application:
Timers
Timer Reload Mode Bit 9
0 = Timer operates as a free
running counter
1 = Timer is reloaded when
selected condition occurs
Direction Bit 11
0 = TIO pin is input
1 = TIO pin is output
Data Input Bit 12
0 = Zero read on TIO pin
1 = One read on TIO pin
Data Output Bit 13
0 = Zero written to TIO pin
1 = One written to TIO pin
Prescaled Clock Enable Bit 15
0 = Clock source is CLK/2 or TIO
1 = Clock source is prescaler output
Timer Compare Flag Bit 21
0 = "1" has been written to TCSR(TCF),
or timer compare interrupt serviced
1 = Timer Compare has occurred
Timer Overflow Flag Bit 20
0 = "1" has been written to TCSR(TOF),
or timer Overflow interrupt serviced
1 = Counter wraparound has occurred
23 22 21 20
19 18 17 16
*
*
TCF
TOF
*
0
0
Timer Control/Status Register TCSR0:$FFFF8F Read/Write
Reset = $000000
Figure B-21. Timer Control/Status Register (TCSR)
B-32
Inverter Bit 8
0 = 0- to-1 transitions on TIO input increment the counter,
or high pulse width measured, or high pulse output on TIO
1 = 1-to-0 transitions on TIO input increment the counter,
or low pulse width measured, or low pulse output on TIO
15 14 13 12 11 10 9
*
*
*
PCE
*
DO
0
0
0
0
0
TCSR1:$FFFF8B Read/Write
TCSR2:$FFFF87 Read/Write
DSP56303 User's Manual
Date:
Programmer:
Timer Control Bits 4–7 (TC[3–0])
TC (3:0)
TIO
0000
GPIO
0001
Output
0010
Output
0011
Input
0100
Input
0101
Input
0110
Input
0111
Output
1000
1001
Output
1010
Output
1011
1100
1101
1110
1111
Timer Overflow Interrupt Enable Bit 1
0 = Overflow Interrupts Disabled
1 = Overflow Interrupts Enabled
Timer Compare Interrupt Enable Bit 2
0 = Compare Interrupts Disabled
1 = Compare Interrupts Enabled
8
7
DI
DIR
*
TRM INV
TC3
TC2
0
*
Sheet 2 of 3
Clock
Mode
Internal
Timer
Internal
Timer Pulse
Internal
Timer Toggle
External
Event Counter
Internal
Input Width
Internal
Input Period
Internal
Capture
Internal
Pulse Width Modulation
Reserved
Internal
Watchdog Pulse
Internal
Watchdog Toggle
Reserved
Reserved
Reserved
Reserved
Reserved
Timer Enable Bit 0
0 = Timer Disabled
1 = Timer Enabled
6
5
4
3
2
1
TC1
TC0
*
TCIE TQIE
TE
0
= Reserved, Program as 0
0

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