Table of Contents
Advertisement
2.6
Interrupt and Mode Control ................................................................................................... 2-9
2.7
Host Interface (HI08)........................................................................................................... 2-10
2.7.1 Host Port Usage Considerations .......................................................................................... 2-10
2.7.2 Host Port Configuration....................................................................................................... 2-11
2.8
Enhanced Synchronous Serial Interface 0 (ESSI0) ............................................................. 2-15
2.9
Enhanced Synchronous Serial Interface 1 (ESSI1) ............................................................. 2-17
2.10
Serial Communication Interface (SCI) ................................................................................ 2-19
2.11
Timers .................................................................................................................................. 2-20
2.12
JTAG/OnCE Interface ......................................................................................................... 2-21
3
Chapter
3.1
Program Memory Space ........................................................................................................ 3-1
3.1.1 Internal Program Memory .................................................................................................... 3-2
3.1.2 Memory Switch Modes-Program Memory ......................................................................... 3-2
3.1.3 Instruction Cache ................................................................................................................... 3-2
3.1.4 Program Bootstrap ROM ....................................................................................................... 3-3
3.2
X Data Memory Space........................................................................................................... 3-3
3.2.1 Internal X Data Memory........................................................................................................ 3-3
3.2.2 Memory Switch Modes-X Data Memory ........................................................................... 3-3
3.2.3 Internal I/O Space-X Data Memory .................................................................................... 3-4
3.3
Y Data Memory Space........................................................................................................... 3-4
3.3.1 Internal Y Data Memory........................................................................................................ 3-4
3.3.2 Memory Switch Modes-Y Data Memory ........................................................................... 3-4
3.3.3 External I/O Space-Y Data Memory................................................................................... 3-5
3.4
Dynamic Memory Configuration Switching ......................................................................... 3-5
3.5
Sixteen-Bit Compatibility Mode Configuration .................................................................... 3-6
3.6
RAM Configuration Summary .............................................................................................. 3-6
3.7
Memory Maps........................................................................................................................ 3-7
4
Chapter
4.1
Operating Modes.................................................................................................................... 4-2
4.2
Bootstrap Program ................................................................................................................. 4-8
4.3
Central Processor Unit (CPU) Registers................................................................................ 4-9
4.3.1 Status Register (SR)............................................................................................................... 4-9
4.3.2 Operating Mode Register (OMR) ........................................................................................ 4-15
4.4
Configuring Interrupts ......................................................................................................... 4-18
4.4.1 Interrupt Priority Registers (IPRC and IPRP)...................................................................... 4-19
4.4.2 Interrupt Table Memory Map .............................................................................................. 4-20
4.4.3 Processing Interrupt Source Priorities Within an IPL ......................................................... 4-22
4.5
PLL Control Register (PCTL) ............................................................................................. 4-24
4.6
Bus Interface Unit (BIU) Registers ..................................................................................... 4-25
4.6.1 Bus Control Register............................................................................................................ 4-25
vi
DSP56303 User's Manual
Advertisement
Table of Contents
