Phase-Locked Loop Control Register (Pctl - Motorola DSP56303 User Manual

Programming Sheets
Application:
PLL
Predivision Factor Bits (PD0–PD3)
PD3–PD0 Predivision Factor PDF
$0
$1
$2
•
•
•
$F
Clock Output Disable (COD)
0 = 50% Duty Cycle Clock
1 = Pin Held In High State
PSTP and PEN Relationship
PSTP PEN
0
1
1
23 22 21 20 19 18 17 16
PD3 PD2 PD1 PD0 COD
PLL Control Register (PCTL)
Reset = $000000
Figure B-5. Phase-Locked Loop Control Register (PCTL)
B-16
1
2
3
•
•
•
16
Operation During STOP
PLL Oscillator
1 Disabled Disabled
0 Disabled Enabled
1 Enabled Enabled
15 14 13 12 11 10 9
PEN PSTP XTLD XTLR DF2 DF1
X:$FFFFFD Read/Write
DSP56303 User's Manual
XTAL Disable Bit (XTLD)
0 = Enable Xtal Oscillator
1 = EXTAL Driven From
An External Source
Crystal Range Bit (XTLR)
0 = External Xtal Freq > 200KHz
1 = External Xtal Freq < 200KHz
Division Factor Bits (DF0–DF2)
DF2–DF0
$0
$1
$2
•
•
•
$7
MF11–MF0
8 7
DF0 MF11 MF10 MF9 MF8 MF7
Date:
Programmer:
Sheet 1 of 1
Division Factor DF
0
2
1
2
2
2
•
•
•
7
2
Multiplication Factor Bits MF0–MF11
Multiplication Factor MF
$000 1
$001 2
$002 3
• •
• •
• •
$FFF 4095
$FFF 4096
6 5 4 3 2 1
MF6 MF5 MF4 MF3 MF2 MF1 MF0
0