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DMA Three-Dimensional Mode (D3D) 4-36
DMA Transfer Mode (DTM) 4-33
DMA Destination Space (DDS) bit 4-37
DMA Interrupt Enable (DIE) bit 4-33
DMA Request Source (DRS) bit 4-36
DMA Source Space (DSS) bit 4-37
DMA Three-Dimensional Mode (D3D) bit 4-36
DMA Transfer Mode (DTM) bit 4-33
DO FOREVER (FV) Flag bit 4-11
DO loop 1-8
Do Loop Flag (LF) bit 4-11
double data strobe mode 2-2
Double Host Request (HDRQ) bit 6-9
Double-Precision Multiply Mode (DM) bit 4-12
DRAM Control Register (DCR) 4-25
Bit Definitions 4-28
Bus Column In-Page Wait State (BCW) 4-29
Bus DRAM Page Size (BPS) 4-29
Bus Mastership Enable (BME) 4-29
Bus Page Logic Enable (BPLE) 4-29
Bus Refresh Enable (BREN) 4-28
Bus Refresh Prescaler (BRP) 4-28
Bus Refresh Rate (BRF) 4-28
Bus Row Out-of-Page Wait States (BRW) 4-29
Bus Software Triggered Reset (BSTR) 4-28
programming sheet B-18
DSP core
programming model 6-13
DSP56300
core 1-1
,
Family Manual 1-1
1-4
DSP56303
Technical Data 1-1
DSP-to-host
data word 6-2
handshaking protocols 6-2
interrupts 6-3
mapping 6-2
transfer modes 6-2
,
transfers 6-6
6-21
dynamic memory configuration switching 3-5
E
Enhanced Synchronous Serial Interface (ESSI) 1-13
,
,
2-17
2-18
7-1
24-bit fractional data 7-16
after reset 7-6
Asynchronous mode 7-4
audio enhancements 7-2
byte format 7-13
,
clock generator 7-11
Clock Sources 7-3
codec 7-13
,
6-25
,
4-27
,
6-9
,
,
,
7-11
7-20
7-17
control and time slot registers 7-6
control direction of SC2 I/O signal 7-23
Control Register A (CRA)
Alignment Control (ALC) 7-16
Frame Rate Divider Control (DC) 7-16
Prescale Modulus Select (PM) 7-16
Prescaler Range (PSR) 7-16
programming sheet B-26
Select SCK (SSC1) 7-15
Word Length Control (WL) 7-15
Control Register B (CRB)
Clock Polarity (CKP) 7-22
Clock Source Directions (SCKD) 7-22
Frame Sync Length (FSL) 7-22
Frame Sync Polarity (FSP) 7-22
Frame Sync Relative Timing (FSR) 7-22
Mode Select (MOD) 7-21
programming sheet B-27
Receive Enable (RE) 7-20
Receive Exception Interrupt Enable (REIE) 7-19
Receive Interrupt Enable (RIE) 7-19
Receive Last Slot Interrupt Enable 7-19
Serial Control Direction 0 (SCD0) 7-23
Serial Control Direction 1 (SCD1) 7-23
Serial Control Direction 2 (SCD2) 7-23
Serial Output Flag 0 (OF0) 7-23
Serial Output Flag 1 (OF1) 7-23
Shift Direction (SHFD) 7-22
Synchronous/Asynchronous (SYN) 7-21
Transmit 0 Enable (TE0) 7-20
Transmit 1 Enable (TE1) 7-21
Transmit 2 Enable (TE2) 7-21
Transmit Exception Interrupt Enable
(TEIE) 7-19
Transmit Interrupt Enable (TIE) 7-20
Transmit Last Slot Interrupt Enable (TLIE) 7-19
control registers 7-14
data and control signals 7-3
DMA 7-7
exception configuration 7-9
exceptions 7-7
receive last slot interrupt 7-8
transmit data 7-8
transmit data with exception status 7-8
,
2-2
transmit last slot interrupt 7-8
flags 7-13
frame rate divider 7-10
frame sync
generator 7-17
length 7-12
polarity 7-12
selection 7-11
signal 7-7
word length 7-12
,
,
7-10
7-18
Index-3
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