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Application:
Bus Interface Unit
Bus Address to Compare, Bits 23–12
BAC[11–0] = address to compare to the
external address in order to decide
whether to assert the AA pin
Bus Number of Address Bits to Compare, Bits 11–8
BNC[3–0] = number of bits (from BAC bits) that are
compared to the external address
(Combinations BNC[3–0] = 1111, 1110, 1101 are
reserved.)
23 22 21 20
19 18 17 16
BAC11
BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 BNC3 BNC2 BNC1 BNC0 BAC7
Address Attribute Registers 3 (AAR3)
Address Attribute Registers 2 (AAR2)
Address Attribute Registers 1 (AAR1)
Address Attribute Registers 0 (AAR0)
Reset = $000000
Figure B-8. Address Attribute Registers (AAR[3–0])
15 14 13 12 11 10 9
X:$FFFFF6 Read/Write
X:$FFFFF7 Read/Write
X:$FFFFF8 Read/Write
X:$FFFFF9 Read/Write
Programming Reference
Programming Sheets
Date:
Programmer:
Bus Packing Enable, Bit 7
0 = Disable internal packing/unpacking logic
1 = Enable internal packing/unpacking logic
Bus Y Data Memory Enable, Bit 5
0 = Disable AA pin and logic during
external Y data space accesses
1 = Enable AA pin and logic during
external Y data space accesses
Bus X Data Memory Enable, Bit 4
0 = Disable AA pin and logic during
external X data space accesses
1 = Enable AA pin and logic during
external X data space accesses
Bus Program Memory Enable, Bit 3
0 = Disable AA pin and logic during
external program space accesses
1 = Enable AA pin and logic during
external program space accesses
Bus Address Attribute Polarity, Bit 2
AA/RAS
0 =
signal is active low
AA/RAS
1 =
signal is active high
Bus Access Type, Bits 1–0
BAT[1–0]
Encoding
00
Reserved
01
SRAM access
10
DRAM access
11
Reserved
8
7
6
5
4
3
BYEN BXEN BPEN BAAP BAT1 BAT0
*
0
= Reserved, Program as 0
*
Sheet 3 of 3
2
1
0
B-19
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