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TX 1
CRB(TE1)
SCn0
Sync:
TX 1, or
Flag0
Async:
CRB(SCD0)
RX clk
SCKn
Sync:
TX/RX clk
Async:
CRB(SCKD)
TX clk
/2
F
CORE
Figure 7-3. ESSI Clock Generator Functional Block Diagram
RX Word
CRA(DC4:0)
Clock
/1 to /32
0
31
Receive
Control
Logic
These signals are
identical in sync mode.
CRB(FSL[1–0])
CRB(FSR)
TX Word
CRA(DC4–0)
Clock
/1 to /32
0
31
Transmit
Control
Logic
Figure 7-4. ESSI Frame Sync Generator Functional Block Diagram
or
Flag0 Out
Flag0 In
CRB(OF0)
SSISR(IF0)
(Sync Mode)
(Sync Mode)
SCD0 = 0
CRB(SYN) =
SYN = 0
SCD0 = 1
Internal Bit Clock
CRA(PSR)
CRA(PM7:0)
/1 or /8
/1 to /256
1
0
0
(Opposite
from SSI)
CRB(FSL1)
CRB(FSR)
Internal Rx Frame Sync
Sync-
Type
CRB(SCD1) = 1
CRB(SYN) = 0
Receive
Frame Sync
SCD1 =
SYN =
Internal TX Frame Sync
Sync
Type
Transmit
Frame Sync
Enhanced Synchronous Serial Interface (ESSI)
CRA(WL2–0)
/8, /12, /16, /24,
0
SYN = 0
RX Shift Register
RCLOCK
SYN = 1
CRA(WL2–0)
TCLOCK
/8, /12, /16, /24,
0
TX Shift Register
Note:1. F
CORE
internal clock frequency.
2. ESSI internal clock range:
min = F
255
max = F
3. 'n' in signal name is ESSI # (0 or 1)
SYN = 0
SYN = 1
Flag1 In
TX 2,
SSISR(IF1)
CRB(TE2)
(Sync Mode)
ESSI Programming Model
RX
Word
Clock
1
2
3 4,5
TX
Word
Clock
1
2
3 4,5
is the DSP56300 core
/4096
OSC
/4
OSC
CRB(SCD1)
SCn1
Sync:
TX 2 Flag1,
or drive enb.
Async:
RX F .S.
Flag1 Out,
or drive enb.
CRA(SSC1)
CRB(OF1)
(Sync Mode)
CRB(SCD2)
SCn2
Sync:
TX/RX F.S.
Async:
TX F.S.
7-17
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