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General-Purpose Input/Output (GPIO) 1-12
functions 6-4
Host Data Direction Register (HDDR) 6-13
Host Data Register (HDR) 6-13
Port B 5-7
Port C 5-8
Port D 5-8
Port E 5-9
Global Data Bus (GDB) 1-10
Ground 2-4
PLL 2-4
H
HACK signal 6-20
handshaking mechanisms
HI08 6-6
hardware stack 1-8
HI08 1-12
ISR
Transmit Data Register Empty 6-29
HI08 Interrupt Priority Level (HPL) bits 4-19
Host Acknowledge Enable (HAEN) bit 6-20
Host Acknowledge Polarity (HAP) bit 6-18
Host Address Line 8 Enable (HA8EN) 6-20
Host Address Line 9 Enable (HA9EN) 6-20
Host Address Strobe Polarity (HASP) bit 6-19
Host Base Address Register (HBAR) 6-13
programming sheet B-22
Host Chip Select Enable (HCSEN) bit 6-20
Host Chip Select Polarity (HSCP) bit 6-18
Host Command (HC) bit 6-27
Host Command Interrupt Enable (HCIE) bit 6-14
Host Command Pending (HCP) bit 6-15
Host Control Register (HCR) 6-13
Host Command Interrupt Enable (HCIE) 6-14
Host Flags 2,3 (HF) 6-14
Host Receive Interrupt Enable (HRIE) 6-15
Host Transmit Interrupt Enable (HTIE) 6-14
programming sheet B-23
Host Data Direction Register (HDDR) 6-4
programming sheet B-34
Host Data Direction Register (HDRR) 6-33
Host Data Register (HDR) 6-13
programming sheet B-34
Host Data Strobe Polarity (HDSP) bit 6-19
Host Dual Data Strobe (HDDS) bit 6-19
Host Enable (HEN) bit 6-19
Host Flag 0 (HF0) bit 6-25
Host Flag 1 (HF1) bit 6-25
Host Flag 2 (HF2) bit 6-28
Host Flag 3 (HF3) bit 6-28
Host Flags 0, 1 (HF) bits 6-15
Host Flags 2,3 (HF) bits 6-14
,
,
2-2
2-20
,
6-33
,
6-33
,
7-20
,
,
6-17
6-33
,
,
6-14
6-32
,
,
6-13
6-16
,
,
6-16
6-33
Host GPIO Port Enable (HGEN) bit 6-20
,
Host Interface (HI08) 2-2
chip-select logic 6-17
Command Vector Register (CVR) 6-8
Host Command (HC) 6-27
Host Vector (HV) 6-27
programming sheet B-24
configuring host request mode 6-9
control operating mode 6-18
core communication with HI08 registers 6-13
core interrupts
host command 6-8
receive data register full 6-8
transmit data empty 6-8
data registers 6-23
data strobe 6-4
Direct Memory Access (DMA) 6-9
DMA transfers and host bus 6-9
double-buffered mechanism 6-6
DSP core 6-6
programming model 6-13
DSP core interrupts 6-7
DSP interrupt routines 6-23
DSP-side
control registers 6-13
data registers 6-13
registers after reset 6-22
DSP-to-host
data word 6-2
handshaking protocols 6-2
interrupts 6-3
mapping 6-2
transfer modes 6-2
,
transfers 6-6
6-21
dual host request enabled 6-10
dual-strobe mode 6-21
enabling host requests 6-9
external host address inputs 6-30
external host programmer's model 6-23
four kinds of reset 6-31
four reset types 6-22
general-purpose flags for host-DSP
communication 6-7
GPIO configuration options 6-16
GPIO functions 6-4
HACK signal 6-20
HACK/HRRQ handshake flags 6-23
handshaking mechanisms 6-6
handshaking protocols 6-6
choosing 6-6
Core DMA access 6-6
host request 6-6
interrupts 6-6
pros and cons of polling 6-7
,
,
,
,
2-10
2-11
2-13
2-14
6-1
,
6-23
Index-5
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