Bus Control Register (Bcr - Motorola DSP56303 User Manual

Application:
Bus Interface Unit
NOTE: All BCR bits are read/write control bits.
Bus Request Hold, Bit 23
0 = BR pin is asserted only for attempted
or pending access
1 = BR pin is always asserted
Bus Lock Hold, Bit 22
0 = BL pin is asserted only for attempted read-
write modify external access
1 = BL pin is always asserted
Bus State, Bit 21
0 = DSP is not bus master
1 = DSP is bus master
23 22 21 20 19 18 17 16
BRH BLH BBS BDFW[4–0]

Bus Control Register (BCR)

Reset = $1FFFFF
15 14 13 12 11 10 9
BA3W[2–0] BA2W[2–0]
X:$FFFFFB Read/Write
Figure B-6. Bus Control Register (BCR)
Programming Reference
Programming Sheets
Date:
Programmer:
Default Area Wait Control, Bits 20–16
Area 3 Wait Control, Bits 15–13
Area 2 Wait Control, Bits 12–10
Area 1 Wait Control, Bits 9–5
Area 0 Wait Control, Bits 4– 0
These read/write control bits define
the number of wait states inserted
into each external SRAM access to
the designated area. The value of
these bits should not be programmed
as zero.
Bits Bit Name # of Wait States
20–16 BDFW[4–0]
15–13 BA3W[2–0]
12–10 BA2W[2–0]
9–5 BA1W[4–0]
4–0 BA0W[4–0]
8 7 6 5 4 3
BA1W[4–0] BA0W[4–0]
Sheet 1 of 3
0–31
0–7
0–7
0–31
0–31
2 1 0
B-17