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4.3.2
Operating Mode Register (OMR)
The OMR is a read/write register divided into three byte-sized units. The lowest two bytes
(EOM and COM) control the chip's operating mode. The high byte (SCS) controls and
monitors the stack extension. The OMR control bits are shown in Figure 4-2.
Stack Control/Status (SCS)
23
22
21
20
19
PEN MSW[1–0] SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP[1–0] MS
Reset:
0
0
0
0
0
After reset, these bits reflect the corresponding value of the mode input (that is, MODD, MODC, MODB, or MODA,
*
respectively).
Reserved bit. Read as zero; write to zero for future compatibility
The Enhanced Operating Mode (EOM) and Chip Operating Mode (COM) bytes are affected
only by processor reset and by instructions directly referencing the OMR (that is, ANDI, ORI,
and other instructions, such as MOVEC, that specify OMR as a destination). The Stack
Control/Status (SCS) byte is referenced implicitly by some instructions, such as DO, JSR, and
RTI, or directly by the MOVEC instruction. During processor reset, the chip operating mode
bits (MD, MC, MB, and MA) are loaded from the external mode select pins MODD, MODC,
MODB, and MODA respectively. Table 4-3 defines the DSP56303 OMR bits.
Table 4-3. Operating Mode Register (OMR) Bit Definitions
Bit Number
Bit Name
23–21
20
SEN
19
WRP
Extended Operating Mode (EOM)
18
17
16
15
14
13
0
0
0
0
0
0
Figure 4-2. Operating Mode Register (OMR)
Reset Value
0
Reserved. Write to 0 for future compatibility.
0
Stack Extension Enable
Enables/disables the stack extension in data memory. If the SEN bit is set,
the extension is enabled. Hardware reset clears this bit, so the default out
of reset is a disabled stack extension.
0
Stack Extension Wrap Flag
Set when copying from the on-chip hardware stack (System Stack
Register file) to the stack extension memory begins. You can use this flag
during the debugging phase of the software development to evaluate and
increase the speed of software-implemented algorithms. The WRP flag is
a sticky bit (that is, cleared only by hardware reset or by an explicit
MOVEC operation to the OMR).
Core Configuration
Central Processor Unit (CPU) Registers
12
11
10
9
8
7
0
0
0
1
1
0
Description
Chip Operating Mode (COM)
6
5
4
3
2
SD
EBD MD MC MB MA
0
0
0
*
*
1
0
*
*
4-15
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