Triple Timer Module Block Diagram; Individual Timer Block Diagram - Motorola DSP56303 User Manual

Overview
9.1.1

Triple Timer Module Block Diagram

Figure 9-1 shows a block diagram of the triple timer module. This module includes a 24-bit
Timer Prescaler Load Register (TPLR), a 24-bit Timer Prescaler Count Register (TPCR), and
three timers. Each timer can use the prescaler clock as its clock source.
GDB
24
TPLR
Timer Prescaler
Load Register
24-bit Counter
CLK/2
9.1.2

Individual Timer Block Diagram

Figure 9-2 shows the structure of an individual timer block. The DSP56303 treats each timer
as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data
memory space. The three timers are identical in structure and function. Either standard polled
or interrupt programming techniques can be used to service the timers. A single, generic timer
is discussed in this chapter. Each timer includes the following:
n
24-bit counter
n
24-bit read/write Timer Control and Status Register (TCSR)
n
24-bit read-only Timer Count Register (TCR)
n
24-bit write-only Timer Load Register (TLR)
n
24-bit read/write Timer Compare Register (TCPR)
n
Logic for clock selection and interrupt/DMA trigger generation.
9-2
24
TPCR
Timer Prescaler
Count Register
TIO0 TIO1 TIO2
Figure 9-1. Triple Timer Module Block Diagram
DSP56303 User's Manual
24
Timer 0
Timer 1
Timer 2
24