Essi Data And Control Signals; Serial Transmit Data Signal (Std); Serial Receive Data Signal (Srd); Serial Clock (Sck) - Motorola DSP56303 User Manual

7.2

ESSI Data and Control Signals

Three to six signals are required for ESSI operation, depending on the operating mode
selected. The serial transmit data (
fully synchronized to the clock if they are programmed as transmit-data signals.
7.2.1

Serial Transmit Data Signal (STD)

The signal transmits data from the serial transmit shift register.
STD
data is transmitted from the TX0 shift register. With an internally-generated bit clock, the
signal becomes a high impedance output signal for a full clock period after the last data bit is
transmitted if another data word does not follow immediately. If sequential data words are
transmitted, the
STD
programmed as a GPIO signal (
7.2.2

Serial Receive Data Signal (SRD)

receives serial data and transfers the data to the receive shift register.
SRD
programmed as a GPIO signal (
7.2.3

Serial Clock (SCK)

is a bidirectional signal providing the serial bit rate clock for the ESSI interface. The
SCK
signal is a clock input or output used by all the enabled transmitters and receivers in
Synchronous modes or by all the enabled transmitters in Asynchronous modes. See Table 7-1
for details. can be programmed as a GPIO signal (
SCK
SYN SCKD
0 0
0 0
0 1
0 1
1 0
1 1
Note: Although an external serial clock can be independent of and asynchronous to the
DSP system clock, the external ESSI clock frequency must not exceed F
each ESSI phase must exceed the minimum of 1.5
sourced ESSI clock frequency must not exceed F
) signal and serial control (
STD
signal does not assume a high-impedance state. The
) when the ESSI
P5
) when the
P4
Table 7-1. ESSI Clock Sources
SCD0 RX Clock Source
Asynchronous
0 EXT, SC0
1 INT
0 EXT, SC0
1 INT
Synchronous
0/1 EXT, SCK
0/1 INT
Enhanced Synchronous Serial Interface (ESSI)
SC0
function is not in use.
STD
function is not in use.
SRD
) when not used as the ESSI clock.
P3
RX Clock
TX Clock Source
Out
— EXT, SCK
SC0 EXT, SCK
— INT
SC0 INT
— EXT, SCK
SCK INT
CLKOUT
/4.
core
ESSI Data and Control Signals
and ) signals are
SC1
is an output when
STD
signal can be
STD
can be
SRD
TX Clock Out
—
—
SCK
SCK
—
SCK
/3, and
core
cycles. The internally
STD
7-3