Host Data Direction Register (Hddr); Host Data Register (Hdr); Host Data Direction Register (Hddr) (X:$Ffffc8); Host Data Register (Hdr) (X:$Ffffc8) - Motorola DSP56303 User Manual

DSP Core Programming Model
Table 6-9. Host Status Register (HSR) Bit Definitions (Continued)
Bit Number Bit Name
0 HRDF
6.6.3

Host Data Direction Register (HDDR)

The HDDR controls the direction of the data flow for each of the HI08 signals configured as
GPIO. Even when the HI08 functions as the host interface, its unused signals can be
configured as GPIO signals. For information on the HI08 GPIO configuration options, see
Section 6.2, Host Port Signals, on page 6-3. If Bit DRxx is set, the corresponding HI08
signal is configured as an output signal. If Bit DRxx is cleared, the corresponding HI08 signal
is configured as an input signal. Hardware and software reset clear the HDDR bits.
15 14 13 12
DR15 DR14 DR13 DR12 DR11 DR10 DR9
Figure 6-8. Host Data Direction Register (HDDR) (X:$FFFFC8)
6.6.4

Host Data Register (HDR)

The HDR register holds the data value of the corresponding bits of the HI08 signals
configured as GPIO signals. The functionality of Dxx depends on the corresponding HDDR
bit (that is, DRxx).The host processor can not access the Host Data Register (HDR)
15 14 13 12
D15 D14 D13 D12
Figure 6-9. Host Data Register (HDR) (X:$FFFFC8)
HDDR
DRxx
0 Read-only bit—The value read is the binary value of
the signal. The corresponding signal is configured as
an input.
1 Read/write bit— The value written is the value read.
The corresponding signal is configured as an output
and is driven with the data written to Dxx.
1. Defined by the selected configuration.
6-16
Reset Value
0 Host Receive Data Full
Indicates that the host receive data register (HRX) contains data from the
host processor. HRDF is set when data is transferred from the
TXH:TXM:TXL registers to the HRX register. The host processor can also
clear HRDF using the initialize function.
11 10 9 8
DR8
11 10 9 8
D11 D10 D9 D8
Table 6-10. HDR and HDDR Functionality
1
GPIO Signal
DSP56303 User's Manual
Description
7 6 5 4
DR7 DR6 DR5 DR4
7 6 5 4
D7 D6 D5 D4
HDR
D xx
Non-GPIO Signal
Read-only bit—Does not contain significant data.
Read/write bit— The value written is the value read.
3 2 1 0
DR3 DR2 DR1 DR0
3 2 1 0
D3 D2 D1 D0
1