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A
adder 1-7
Address Arithmetic Logic Unit (Address ALU) 1-7
Address Attribute Priority Disable (APD) bit 4-16
Address Attribute Registers (AAR) 4-25
Bus Access Type (BAT) 4-32
Bus Address Attribute Polarity (BAAP) 4-31
Bus Address to Compare (BAC) 4-30
Bus Number of Address Bits to Compare (BNC) 4-30
Bus Packing Enable (BPAC) 4-31
Bus Program Memory Enable (BPEN) 4-31
Bus X Data Memory Enable (BXEN) 4-31
Bus Y Data Memory Enable (BYEN) 4-31
programming sheet B-19
Address Generation Unit (AGU) 1-7
Address Mode Wakeup 8-3
Address Trace Enable (ATE) bit 4-16
Address Trace mode 1-5
addressing modes 1-7
Alignment Control (ALC) bit 7-16
Arithmetic Saturation Mode (SM) bit 4-10
Asynchronous Bus Arbitration Enable (ABE) bit 4-16
asynchronous data transfer 8-2
,
Asynchronous mode 7-10
Asynchronous Multidrop mode 8-17
B
barrel shifter 1-6
bit-oriented instructions 5-2
BCHG 5-2
BCLR 5-2
BRCLR 5-2
BRSET 5-2
BSCLR 5-2
BSET 5-2
BSSET 5-2
BTST 5-2
JCLR 5-2
JSCLR 5-2
JSET 5-2
JSSET 5-2
,
bootstrap 3-1
3-3
code 8-8
,
program 4-8
A-1
program options, invoking 4-8
ROM 1-5
,
4-30
,
,
,
8-2
8-15
8-17
8-18
DSP56303 User's Manual
Boundary Scan Register (BSR) 4-38
Burst Mode Enable (BE) bit 4-17
bus
address 2-2
data 2-2
external address 2-6
external data 2-6
internal 1-10
multiplexed 2-2
non-multiplexed 2-2
Bus Access Type (BAT) bits 4-32
Bus Address Attribute Polarity (BAAP) bit 4-31
Bus Address to Compare (BAC) bits 4-30
Bus Area 0 Wait State Control (BA0W) bits 4-27
Bus Area 1 Wait State Control (BA1W) bits 4-27
Bus Area 2 Wait State Control (BA2W) bits 4-26
Bus Area 3 Wait State Control (BA3W) bits 4-26
Bus Column In-Page Wait State (BCW) bit 4-29
Bus Control Register (BCR) 4-25
Bit Definitions 4-26
Bus Area 0 Wait State Control (BA0W) 4-27
Bus Area 1 Wait State Control (BA1W) 4-27
Bus Area 2 Wait State Control (BA2W) 4-26
Bus Area 3 Wait State Control (BA3W) 4-26
Bus Default Area Wait State Control (BDFW) 4-26
Bus Lock Hold (BLH) bit 4-26
Bus Request Hold (BRH) 4-26
Bus Request Hold (BRH) bit 4-26
Bus State (BBS) bit 4-26
programming sheet B-17
Bus Default Area Wait State Control (BDFW) bits 4-26
Bus DRAM Page Size (BPS) bit 4-29
Bus Interface Unit (BIU)
Address Attribute Registers (AAR) 4-25
Bus Control Register (BCR) 4-25
DRAM Control Register (DCR) 4-25
Bus Mastership Enable (BME) bit 4-29
Bus Number of Address Bits to Compare (BNC) bits 4-30
Bus Packing Enable (BPAC) bit 4-31
Bus Page Logic Enable (BPLE) bit 4-29
Bus Program Memory Enable (BPEN) bit 4-31
Bus Refresh Enable (BREN) bit 4-28
Bus Refresh Prescaler (BRP) bit 4-28
Bus Refresh Rate (BRF) bit 4-28
Bus Release Timing (BRT) bit 4-17
Bus Request Hold (BRH) bit 4-26
Bus Row Out-of-Page Wait States (BRW) bit 4-29
Bus Software Triggered Reset (BSTR) bit 4-28
Index-1
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