Motorola DSP56303 User Manual page 319

bit definitions 9-28
Data Input (DI) 9-29
Data Output (DO) 9-29
Direction (DIR) 9-30
,
Inverter (INV) 9-30 9-32
Prescaler Clock Enable (PCE) 9-29
programming sheet B-32
Timer Compare Flag (TCF) 9-29
Timer Compare Interrupt Enable (TCIE) 9-32
Timer Control (TC) 9-31
Timer Enable (TE) 9-32
Timer Overflow Flag (TOF) 9-29
Timer Overflow Interrupt Enable (TOIE) 9-32
Timer Reload Mode (TRM) 9-30
Timer Count Register (TCR) 9-34
Timer Enable (TE) bit 9-32
Timer Interrupt Enable (TMIE) bit 8-13
Timer Interrupt Priority Level (TOL) bits 4-19
Timer Interrupt Rate (STIR) bit 8-12
Timer Load Registers (TLR) 9-4
programming sheet B-33
Timer module
architecture 9-1
timer block diagram 9-2
Timer Overflow Flag (TOF) bit 9-29
Timer Overflow Interrupt Enable (TOIE) bit 9-32
Timer Prescaler Count Register (TPCR) 9-28
bit definitions 9-28
Prescaler Counter Value (PC) 9-28
Timer Prescaler Load Register (TPLR) 9-4
bit definitions 9-27
Prescaler Preload Value (PL) 9-27
Prescaler Source (PS) 9-27
programming sheet B-31
Timer Reload Mode (TRM) bit 9-30
Transmit 0 Enable (TE0) bit 7-20
Transmit 1 Enable (TE1) bit 7-21
Transmit 2 Enable (TE2) bit 7-21
Transmit Byte Registers (TXH, TXM, TXL) 6-6
Transmit Clock Source (TDM) bit 8-19
Transmit Data Empty (TDE) bit 6-7
Transmit Data Register Empty (TDE) bit 7-28
Transmit Data Register Empty (TDRE) bit 8-18
Transmit Data Register Empty (TXDE) bit 6-29
Transmit Data Registers (TX0–TX2) 7-14
Transmit Data Registers (TXH, TXM, TXL) 6-5
Transmit Data signal (TXD) 8-4
Transmit Enable (TE) bits 7-18
Transmit Exception Interrupt Enable (TEIE) bit 7-19
Transmit Frame Sync Flag (TFS) 7-29
Transmit Interrupt Enable (TIE) bit 7-20
Transmit Last Slot Interrupt Enable (TLIE) bit 7-19
Transmit Request Enable (TREQ) bit 6-26
Transmit Shift Registers 7-30
,
9-33
,
9-27
,
6-30
,
7-33
Transmit Slot Mask Registers (TSMA and TSMB) 7-14
7-33
Transmitter Empty (TRNE) bit 8-18
Transmitter Enable (TE) bit 8-14
Transmitter Ready (TRDY) bit 6-28
Transmitter Underrun Error Flag (TUE) 7-28
triple timer module 1-14
TX clock 7-11
TXD signal 8-4
TXH, TXM, TXL registers 6-30
U
Unnormalized (U) bit 4-14
V
Vector Base Address register (VBA) 1-8
W
Wait standby mode 1-5
Wakeup Mode Select (WAKE) bit 8-15
Wired-OR Mode Select (WOMS) bit 8-14
Word Length Control (WL) bits 7-15
Word Select (WDS) bits 8-16
X
,
X data memory 1-5 3-3
,
X I/O space 3-4 3-5
X Memory Address Bus (XAB) 1-10
X Memory Data Bus (XDB) 1-10
X Memory Expansion Bus 1-10
XTAL Disable (XTLD) bit 4-24
Y
,
Y data memory 1-5 3-4
Y Memory Address Bus (YAB) 1-10
Y Memory Data Bus (YDB) 1-10
Y Memory Expansion Bus 1-10
Z
Zero (Z) bit 4-14
,
Index-13