Motorola DSP56303 User Manual page 273

24-bit digital signal processor
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Table B-2. Internal I/O Memory Map (Continued)(X Data Memory)
Peripheral
16-Bit Address
HI08
$FFC7
$FFC6
$FFC5
$FFC4
$FFC3
$FFC2
$FFC1
$FFC0
Port C
$FFBF
$FFBE
$FFBD
ESSI 0
$FFBC
$FFBB
$FFBA
$FFB9
$FFB8
$FFB7
$FFB6
$FFB5
$FFB4
$FFB3
$FFB2
$FFB1
$FFB0
Port D
$FFAF
$FFAE
$FFAD
24-Bit Address
$FFFFC7
Host Transmit Register (HTX)
$FFFFC6
Host Receive Register (HRX)
$FFFFC5
Host Base Address Register (HBAR)
$FFFFC4
Host Port Control Register (HPCR)
$FFFFC3
Host Status Register (HSR)
$FFFFC2
Host Control Register (HCR)
$FFFFC1
Reserved
$FFFFC0
Reserved
$FFFFBF
Port C Control Register (PCRC)
$FFFFBE
Port C Direction Register (PRRC)
$FFFFBD
Port C GPIO Data Register (PDRC)
$FFFFBC
ESSI 0 Transmit Data Register 0 (TX00)
$FFFFBB
ESSI 0 Transmit Data Register 1 (TX01)
$FFFFBA
ESSI 0 Transmit Data Register 2 (TX02)
$FFFFB9
ESSI 0 Time Slot Register (TSR0)
$FFFFB8
ESSI 0 Receive Data Register (RX0)
$FFFFB7
ESSI 0 Status Register (SSISR0)
$FFFFB6
ESSI 0 Control Register B (CRB0)
$FFFFB5
ESSI 0 Control Register A (CRA0)
$FFFFB4
ESSI 0 Transmit Slot Mask Register A
(TSMA0)
$FFFFB3
ESSI 0 Transmit Slot Mask Register B
(TSMB0)
$FFFFB2
ESSI 0 Receive Slot Mask Register A (RSMA0)
$FFFFB1
ESSI 0 Receive Slot Mask Register B (RSMB0)
$FFFFB0
Reserved
$FFFFAF
Port D Control Register (PCRD)
$FFFFAE
Port D Direction Register (PRRD)
$FFFFAD
Port D GPIO Data Register (PDRD)
Programming Reference
Internal I/O Memory Map
Register Name
B-5

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