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Receive Byte Registers (RXH, RXM, RXL) 6-5
6-30
register banks 6-4
request service from host 6-9
resets
hardware and software 6-4
single-strobe mode 6-21
software polling 6-7
software reset 6-31
STOP command 6-24
STOP instruction 6-31
Stop mode 6-24
timing requirements 6-6
Transmit Byte Registers 6-6
Transmit Byte Registers (TXH, TXM, TXL) 6-30
Transmit Data Registers (TXH, TXM, TXL) 6-5
Transmit Registers (TXH, TXM, TXL) 6-7
vector registers 6-23
Host Litle Endian (HLEND) bit 6-25
Host Multiplexed Bus (HMUX) bit 6-19
host port
configuration 2-11
usage considerations 2-10
Host Port Control Register (HPCR) 6-4
,
6-32
6-33
Host Acknowledge Enable (HAEN) 6-20
Host Acknowledge Polarity (HAP) 6-18
Host Address Line 8 Enable (HA8EN) 6-20
Host Address Line 9 Enable (HA9EN) 6-20
Host Address Strobe Polarity (HASP) 6-19
Host Chip Select Enable (HCSEN) 6-20
Host Chip Select Polarity (HCSP) 6-18
Host Data Strobe Polarity (HDSP) 6-19
Host Dual Data Strobe (HDDS) 6-19
Host Enable (HEN) 6-19
Host GPIO Port Enable (HGEN) 6-20
Host Multiplexed Bus (HMUX) 6-19
Host Request Enable (HREN) 6-20
Host Request Open Drain (HROD) 6-19
Host Request Polarity (HRP) 6-18
programming sheet B-5
host processor address space 6-23
Host Receive (HRX) register 6-6
Host Receive Data Full (HRDF) bit 6-7
Host Receive Interrupt Enable (HRIE) bit 6-15
Host Receive Request (HRRQ) 6-9
host request 6-6
double 2-2
enabling 6-9
single 2-2
Host Request (HREQ) bit 6-28
Host Request Enable (HREN) bit 6-20
host request line 6-4
Host Request Open Drain (HROD) bit 6-19
,
6-6
,
6-13
,
,
,
6-13
6-18
6-22
,
7-20
,
B-22
,
,
,
6-13
6-22
6-33
,
6-16
,
host request pins 6-10
Host Request Polarity (HRP) bit 6-18
Host Status Register (HSR) 6-13
Host Command Pending (HCP) 6-15
Host Flags 0, 1 (HF) 6-15
Host Receive Data Full (HRDF) 6-16
Host Transmit Data Empty (HTDE) 6-15
Host Transmit (HTX) register 6-7
Host Transmit Data Empty (HTDE) bit 6-7
Host Transmit Data Register (HTDR)
programming sheet B-21
Host Transmit Interrupt Enable (HTIE) bit 6-14
Host Vector (HV) bits 6-27
Hosts Interface (HI08)
Interrupt Control Register (ICR)
programming sheet B-24
host-to-DSP transfers 6-6
I
I/O space
X data memory 3-4
Idle Line Flag (IDLE) bit 8-18
Idle Line Interrupt Enable (ILIE) bit 8-13
,
Idle Line Wakeup mode 8-3
Initialize (INIT) bit 6-25
initializing the timer 9-3
instruction cache 1-5
location 3-6
Interface Control Register (ICR) 6-24
Double Host Request (HDRQ) 6-9
Host Flag 0 (HF0) 6-25
Host Flag 1 (HF1) 6-25
Host Little Endian (HLEND) 6-25
Initialize (INIT) 6-25
Receive Request Enable (RREQ) 6-26
Transmit Request Enable (TREQ) 6-26
Interface Status Register (ISR) 6-27
Host Flag 2 (HF2) 6-28
Host Flag 3 (HF3) 6-28
Host Request (HREQ) 6-28
Receive Data Full (RDF) 6-7
Receive Data Register Full (RXDF) 6-29
Transmit Data Empty (TDE) 6-7
Transmit Data Register Empty (TXDE) 6-29
Transmitter Ready (TRDY) 6-28
Interface Vector Register (IVR) 6-29
internal buses 1-10
internal I/O memory map B-3
internal program memory 3-1
,
interrupt 1-8
5-3
configuring 4-18
Host Interface (HI08) 6-6
priorities B-10
,
,
6-15
6-33
,
,
,
6-13
6-21
6-33
,
6-15
,
B-25
,
3-5
,
3-2
,
6-25
,
3-2
,
6-7
Index-7
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