Figure 6-9 Host Data Direction Register (Hddr) (X:$Ffffc8); Figure 6-10 Host Data Register (Hdr) (X:$Ffffc9) - Motorola DSP56309 User Manual

6.5.7 Host Data Direction Register (HDDR)
The HDDR controls the direction of the data flow for each of the HI08 signals configured
as GPIO. It is illustrated in Figure 6-9. Even when the HI08 functions as the host
interface, its unused signals can be configured as GPIO signals. For information on the
HI08 GPIO configuration options, see Section 6.6.8ÑGeneral-Purpose I/O on page 6-30.
If bit DRxx is set, the corresponding HI08 signal is configured as an output signal. If bit
DRxx is cleared, the corresponding HI08 signal is configured as an input signal.
15 14 13
DR15 DR14 DR13 DR12 DR11 DR10

Figure 6-9 Host Data Direction Register (HDDR) (X:$FFFFC8)

6.5.8 Host Data Register (HDR)
The HDR register holds the data value of the corresponding bits of the HI08 signals
configured as GPIO signals. It is illustrated in Figure 6-10. The functionality of the Dxx
bit depends on the corresponding HDDR bit (DRxx), as in Table 6-5. The HDR cannot be
accessed by the host processor.
15 14 13
D15 D14 D13 D12

Figure 6-10 Host Data Register (HDR) (X:$FFFFC9)

MOTOROLA
12 11 10 9
DR9
12 11 10 9
D11 D10 D9
DSP56309UM/D
HI08 DSP Side ProgrammerÕs Model
8 7 6 5
DR8 DR7 DR6 DR5
8 7 6 5
D8 D7 D6 D5
Host Interface (HI08)
4 3 2 1
DR4 DR3 DR2 DR1
4 3 2 1
D4 D3 D2 D1
0
DR0
AA0663
0
D0
AA0664
6-17