Figure 6-16 Hi08 Host Request Structure - Motorola DSP56309 User Manual

7
$2
HREQ 0
Host Request
Asserted
7
$0 INIT 0
HREQ is normally connected to the maskable interrupt input of the host processor. The
host processor acknowledges host interrupts by executing an interrupt service routine.
The host processor can test the two LSBs (RXDF and TXDE) of the ISR register to
determine the interrupt source, as in Figure 6-16. The host processor interrupt service
routine must read or write the appropriate HI08 data register to clear the interrupt.
HREQ/HTRQ and/or HRRQ is deasserted under either of the following conditions:
¥ The enabled request is cleared or masked.
¥ The DSP is reset.
If the host processor is a member of the MC68000 family, there is no need for the
additional step when the host processor reads the ISR to determine how to respond to an
interrupt generated by the DSP56309. Instead, the DSP56309 automatically sources the
contents of the IVR on the data bus when the host processor acknowledges the interrupt
by asserting HACK. The contents of the IVR are placed on the host data bus while
HREQ/TRQ (or HRRQ) and HACK are simultaneously asserted. The IVR data tells the
MC680XX host processor which interrupt routine to execute to service the DSP56309.
Table 6-13 shows the HI08 programming model.
MOTOROLA
0 HF3 HF2 TRDY
0 HF1 HF0 HBEND TREQ

Figure 6-16 HI08 Host Request Structure

DSP56309UM/D
Servicing the Host Interface
Status
0
TXDE RXDF ISR
0
RREQ ICR
Enable
Host Interface (HI08)
HRRQ
HREQ
HTRQ
AA0672
6-33