Debugging Resources - Motorola DSP56309 User Manual

On-Chip Emulation Module

Debugging Resources

10.8.3 OnCE GDB Register (OGDBR)
The OGDBR is a 16-bit latch that can only be read through the JTAG port. The OGDBR is
not actually required for restoring the pipeline status but is required as a means of
passing information between the chip and the external command controller. The
OGDBR is mapped on the X internal I/O space at address $FFFC. Whenever the external
command controller needs the contents of a register or memory location, it forces the
chip to execute an instruction that brings that information to the OGDBR. Then the
contents of the OGDBR are delivered serially to the external command controller by the
command READ GDB REGISTER.
10.9 DEBUGGING RESOURCES
To ease debugging activity and keep track of program flow, the DSP56300 core provides
a number of on-chip dedicated resources. There are three read-only PAB registers that
give pipeline information when debug mode is entered, and a trace buffer that stores the
address of the last instruction that was executed, as well as the addresses of the last 12
change-of-flow instructions.
10.9.1 OnCE PAB Register for Fetch (OPABFR)
The OPABFR is a 16-bit register that stores the address of the last instruction whose fetch
was started before debug mode was entered. The OPABFR can only be read through the
JTAG port. This register is not affected by the operations performed during debug mode.
10.9.2 PAB Register for Decode (OPABDR)
The OPABDR is a 16-bit register that stores the address of the instruction currently on
the PDB. This is the instruction whose fetch was completed before the chip has entered
debug mode. The OPABDR can only be read through the JTAG port. This register is not
affected by the operations performed during debug mode.
10.9.3 OnCE PAB Register for Execute (OPABEX)
The OPABEX is a 16-bit register that stores the address of the instruction currently in the
instruction latch. This is the instruction that would have been decoded and executed if
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