Figure 11-5 Bypass Register - Motorola DSP56309 User Manual

11.3.2.6 ENABLE_ONCE(B[3:0] = 0110)
The ENABLE_ONCE instruction is not included in the IEEE 1149.1 standard. It is
provided as a public instruction to allow you to perform system debug functions. When
the ENABLE_ONCE instruction is decoded the TDI and TDO signals are connected
directly to the OnCE registers. The particular OnCE register connected between TDI and
TDO at a given time is selected by the OnCE controller depending on the OnCE
instruction being currently executed. All communication with the OnCE controller is
done through the Select-DR-Scan path of the JTAG TAP controller. See
Section 10ÑOn-Chip Emulation Module for more information.
11.3.2.7 DEBUG_REQUEST(B[3:0] = 0111)
The DEBUG_REQUEST instruction is not included in the IEEE 1149.1 standard. It is
provided as a public instruction to allow you to generate a debug request signal to the
DSP56300 core. When the DEBUG_REQUEST instruction is decoded, the TDI and TDO
signals are connected to the instruction registers. Due to the fact that in the Capture-IR
state of the TAP the OnCE status bits are captured in the Instruction shift register, the
external JTAG controller must continue to shift-in the DEBUG_REQUEST instruction
while polling the status bits that are shifted-out until debug mode is entered
(acknowledged by the combination 11 on OS1ÐOS0). After the acknowledgment of
debug mode is received, the external JTAG controller must issue the ENABLE_ONCE
instruction to allow the user to perform system debug functions.
11.3.2.8 BYPASS (B[3:0] = 1111)
The BYPASS instruction selects the single-bit bypass register, as shown in Figure 11-5.
This choice creates a shift-register path from TDI to the bypass register, and finally to
TDO, circumventing the BSR. This instruction is used to enhance test efficiency when a
component other than the DSP56300 core-based device becomes the device under test.
When the bypass register is selected by the current instruction, the shift-register stage is
set to a logical 0 on the rising edge of TCK in the Capture-DR controller state. Therefore,
the first bit shifted out after selecting the bypass register is always a logical 0.
Shift DR
From TDI
MOTOROLA
G1
0
1
Mux
1

Figure 11-5 Bypass Register

DSP56309UM/D
D
C
CLOCKDR
JTAG Port
TAP Controller
To TDO
AA0115
11-11