Motorola DSP56309 User Manual page 267

Triple Timer Module
Timer Operational Modes
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated. At the same time, a pulse is output on the TIO signal with a pulse width equal
to the timer clock period. The pulse polarity is determined by the value of the INV bit. If
the INV bit is set, the pulse polarity is high (logical 1). If the INV bit is cleared, the pulse
polarity is low (logical 0).
The counter contents can be read at any time by reading the TCR. The counter is
reloaded whenever the TLR is written with a new value while the TE bit is set.
Note: In this mode, internal logic preserves the TIO value and direction for an
additional 2.5 internal clock cycles after a DSP56309 hardware RESET signal is
asserted. This insures that a valid RESET signal is generated when the TIO
signal is used to reset the DSP56309.
9.4.4.2 Watchdog Toggle (Mode 10)
Bit Settings
TC3 TC2 TC1
1 0 1
In this mode, the timer toggles an external signal after preset period.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TPCR. The counter is loaded with the TLR value on the first
timer clock received from either the DSP56309 internal clock divided by two (CLK/2) or
the prescaler clock output. Each subsequent timer clock increments the counter. The TIO
signal is set to the value of the INV bit.
When the counter equals the value in the TCPR, the TCF bit in the TCSR is set, and a
compare interrupt is generated if the TCIE bit is also set. If the TRM bit is set, the counter
is loaded with the TLR value on the next timer clock and the count is resumed. If the
TRM bit is cleared, the counter continues to be incremented on each subsequent timer
clock.
When counter overflow has occurred, the polarity of the TIO output signal is inverted,
the TOF bit in the TCSR is set, and an overflow interrupt is generated if the TOIE bit is
also set. The TIO polarity is determined by the INV bit.
The counter is reloaded whenever the TLR is written with a new value while the TE bit is
set. This process is repeated until the timer is disabled by clearing the TE bit. The counter
contents can be read at any time by reading the TCR register.
9-26
TC0 Mode NAME
0 10 Toggle
DSP56309UM/D
Mode Characteristics
Function
Watchdog
TIO Clock
Output Internal
MOTOROLA