Pipeline Information And Ogdb Register - Motorola DSP56309 User Manual

On-Chip Emulation Module

Pipeline Information and OGDB Register

10.7.6 Software Request During Normal Activity
Upon executing the DSP56300 core instruction DEBUG (or DEBUGcc when the specified
condition is true), the chip enters debug mode after the instruction following the DEBUG
instruction has entered the instruction latch.
10.7.7 Enabling Trace Mode
When Trace mode is enabled and the OTC is greater than zero, the OTC is decremented
after each instruction execution. Execution of an instruction when the value in the OTC
is 0 causes the chip to enter debug mode after completing the execution of the
instruction. Only instructions actually executed cause the OTC to decrement. An aborted
instruction does not decrement the OTC and does not cause the chip to enter debug
mode.
10.7.8 Enabling Memory Breakpoints
When the memory breakpoint mechanism is enabled with a breakpoint counter value of
0, the chip enters debug mode after completing the execution of the instruction that
caused the memory breakpoint to occur. In case of breakpoints on executed program
memory fetches, the breakpoint is acknowledged immediately after the execution of the
fetched instruction. In case of breakpoints on accesses to X, Y or program memory spaces
by MOVE instructions, the breakpoint is acknowledged after the completion of the
instruction following the instruction that accessed the specified address.
10.8 PIPELINE INFORMATION AND OGDB REGISTER
To restore the pipeline and to resume normal chip activity upon returning from debug
mode, a number of on-chip registers store the chip pipeline status. Figure 10-9 shows the
block diagram of the pipeline information registers, with the exception of the PAB
registers, which appear in Figure 10-10 on page 10-22.
10-18 DSP56309UM/D MOTOROLA