Motorola DSP56309 User Manual page 220

The word select bits are cleared by either a hardware RESET signal or a software RESET
instruction.
8.3.1.2 SCR SCI Shift Direction (SSFTD) Bit 3
The SSFTD bit determines the order in which the SCI data shift registers shift data in or
out: MSB first when set, LSB first when cleared. The parity and data type bits do not
change their position in the frame; they remain adjacent to the stop bit. SSFTD is cleared
by either a hardware RESET signal or a software RESET instruction.
8.3.1.3 SCR Send Break (SBK) Bit 4
A break is an all-zero word frameÑa start bit 0, characters of all 0s (including any
parity), and a stop bit 0 (i.e., ten or eleven 0s, depending on the mode selected). If SBK is
set and then cleared, the transmitter completes transmission of the current frame, sends
ten or eleven 0s (depending on WDS mode), and reverts to idle or sending data. If SBK
remains set, the transmitter continually sends whole frames of 0s (ten or eleven bits with
no stop bit). At the completion of the break code, the transmitter sends at least one high
(set) bit before transmitting any data to guarantee recognition of a valid start bit. Break
can be used to signal an unusual condition, message, etc. by forcing a frame error, which
is caused by a missing stop bit. Either a hardware RESET signal or a software RESET
instruction clears SBK.
8.3.1.4 SCR Wakeup Mode Select (WAKE) Bit 5
When WAKE is cleared, the wakeup on idle line mode is selected. In the wakeup on idle
line mode, the SCI receiver is reenabled by an idle string of at least ten or eleven
(depending on WDS mode) consecutive 1s. The transmitterÕs software must provide this
idle string between consecutive messages. The idle string cannot occur within a valid
message because each word frame contains a start bit that is 0.
When WAKE is set, the wakeup on address bit mode is selected. In the wakeup on
address bit mode, the SCI receiver is reenabled when the last (eighth or ninth) data bit
received in a character (frame) is 1. The ninth data bit is the address bit (R8) in the 11-bit
multidrop mode; the eighth data bit is the address bit in the 10-bit asynchronous and
11-bit asynchronous with parity modes. Thus, the received character is an address that
has to be processed by all sleeping processorsÑthat is, each processor has to compare
the received character with its own address and decide whether to receive or ignore all
following characters. Either a hardware RESET signal or a software RESET instruction
clears WAKE.
8.3.1.5 SCR Receiver Wakeup Enable (RWU) Bit 6
When RWU is set and the SCI is in an asynchronous mode, the wakeup function is
enabledÑthat is, the SCI is asleep, and can be awakened by the event defined by the
WAKE bit. In the sleep state, all interrupts and all receive flags except IDLE are disabled.
MOTOROLA
Serial Communication Interface (SCI)
DSP56309UM/D
SCI Programming Model
8-9