Introduction; Triple Timer Module Architecture - Motorola DSP56309 User Manual

9.1

INTRODUCTION

This section describes the internal triple timer module in the DSP56309. Each timer has a
single signal that can be used as a GPIO signal or as a timer signal. These three timers
can be used to generate timed pulses or as pulse width modulators. They can also be
used as an event counter, to capture an event, or to measure the width or period of a
signal.
9.2

TRIPLE TIMER MODULE ARCHITECTURE

The timer module is composed of a common 21-bit prescaler and three independent and
identical general purpose 24-bit timer/event counters, each having its own register set.
Each timer can use internal or external clocking and can interrupt the DSP56309 after a
specified number of events (clocks) or can signal an external device after counting
internal events. Each timer can also be used to trigger DMA transfers after a specified
number of events (clocks) has occurred. Each timer connects to the external world
through one bidirectional signal, designated TIO0ÐTIO2 for Timers 0Ð2, respectively.
When the TIO signal is configured as input, the timer functions as an external event
counter or measures external pulse width/signal period. When the TIO signal is used as
output, the timer functions as a timer, a watchdog timer, or a pulse width modulator.
When the TIO signal is not used by the timer, it can be used as a GPIO signal (also called
TIO0ÐTIO2).
9.2.1 Triple Timer Module Block Diagram
Figure 9-1 shows a block diagram of the triple timer module. This module includes a
24-bit timer prescaler load register (TPLR), a 24-bit timer prescaler count register
(TPCR), a 21-bit prescaler clock counter, and three timers. Each of the three timers can
use the prescaler clock as its clock source.
MOTOROLA DSP56309UM/D
Triple Timer Module
Introduction
9-3