Figure 7-11 Crb Fsl0 And Fsl1 Bit Operation (Fsr = 0) - Motorola DSP56309 User Manual

Serial Clock
RX, TX Frame SYNC
RX, TX Serial Data
NOTE: Frame sync occurs while data is valid.
Serial Clock
RX, TX Frame SYNC
RX, TX Serial Data
NOTE: Frame sync occurs for one bit time preceding the data.
Serial Clock
RX Frame Sync
RXSerial Data
TX Frame SYNC
TX Serial Data
Serial Clock
RX Frame SYNC
RX Serial Data
TX Frame SYNC
TX Serial Data

Figure 7-11 CRB FSL0 and FSL1 Bit Operation (FSR = 0)

MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
Word Length: FSL1 = 0, FSL0 = 0
Data
One Bit Length: FSL1 = 1, FSL0 = 0
Data
Mixed Frame Length: FSL1 = 0, FSL0 = 1
Data
Data
Mixed Frame Length: FSL1 = 1, FSL0 = 1
Data
Data
DSP56309UM/D
ESSI Programming Model
Data
Data
Data
Data
Data
Data
AA0681
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