Table of Contents
Advertisement
Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility
Note:
A hardware RESET signal or a software RESET instruction clears all PDRE
bits.
MOTOROLA
7
6
5
4
13
12
15
14
21
20
23
22
Figure 8-10 Port E Data Register (PDRE)
DSP56309UM/D
Serial Communication Interface (SCI)
GPIO Signals and Registers
3
2
1
0
PD2
PD1
PD0
11
10
9
8
19
18
17
16
AA0697
8-29
Advertisement
Chapters
Table of Contents
