Motorola DSP56309 User Manual page 260

Triple Timer Module
Timer Operational Modes
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated.
The counter contents can be read at any time by reading the TCR.
9.4.1.3 Timer Toggle (Mode 2)
Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 TIO Clock # Function Name
0 0 1 0 Output Internal 0 Timer Toggle
In this mode, the timer periodically toggles the polarity of the TIO signal.
Set the TE bit in the TCR to clear the counter and enable the timer. The value to which
the timer is to count is loaded into the TPCR. The counter is loaded with the TLR value
when the first timer clock signal is received. The TIO signal is loaded with the value of
the INV bit. The timer clock signal can be taken from either the DSP56309 clock divided
by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal
increments the counter.
When the counter value matches the value in the TCPR, the polarity of the TIO output
signal is inverted. The TCF bit in the TCSR is set and a compare interrupt is generated if
the TCIE bit is set.
If the TRM bit is set, the counter is loaded with the value of the TLR when the next timer
clock is received, and the count is resumed. If the TRM bit is cleared, the counter
continues to be incremented on each timer clock.
This process is repeated until the TE bit is cleared, disabling the timer. The counter
contents can be read at any time by reading the TCR.
The TLR value in the TCPR sets the delay between starting the timer and toggling the
TIO signal. To generate output signals with a delay of X clock cycles between toggles,
the TLR value should be set to X/2, and the TRM bit should be set.
This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter
overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
MOTOROLA DSP56309UM/D 9-19