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Host Interface (HI08)
HI08 DSP Side ProgrammerÕs Model
6.5.3.1
HCR Host Receive Interrupt Enable (HRIE) Bit 0
The HRIE bit generates a host receive data interrupt request if the host receive data full
(HRDF) bit in the host status register (HSR, Bit 0), is set. The HRDF bit is set when data is
written to the HRX. If HRIE is cleared, HRDF interrupts are disabled.
6.5.3.2
HCR Host Transmit Interrupt Enable (HTIE) Bit 1
The HTIE bit generates a host transmit data interrupt request if the host transmit data
empty (HTDE) bit in the HSR is set. The HTDE bit is set when data is read from the HTX.
If HTIE is cleared, HTDE interrupts are disabled.
6.5.3.3
HCR Host Command Interrupt Enable (HCIE) Bit 2
The HCIE bit generates a host command interrupt request if the host command pending
(HCP) status bit in the HSR is set. If HCIE is cleared, HCP interrupts are disabled. The
interrupt address is determined by the host command vector register (CVR).
Note:
If more than one interrupt request source is asserted and enabled (e.g., HRDF
is set, HCP is set, HRIE is set, and HCIE is set), the HI08 generates interrupt
requests according to priorities shown in Table 6-4.
6.5.3.4
HCR Host Flags 2,3 (HF[3:2]) Bits 3, 4
HF[3:2] bits are general-purpose flags for DSP-to-host communication. The DSP core sets
and clears them. The values of HF[3:2] are reflected in the interface status register (ISR);
that is, if they are modified by the DSP software, the host processor can read the
modified values by reading the ISR.
These two flags can be used individually or as encoded pairs in a simple DSP-to-host
communication protocol, implemented in both the DSP and the host processor software.
6.5.3.5
HCR Reserved Bits 5-15
These bits are reserved. They are read as 0 and should be written with 0.
6-10
Table 6-4 Host Command Interrupt Priority List
Priority
Highest
Host Command (HCP = 1)
Transmit Data (HTDE = 1)
Lowest
DSP56309UM/D
Interrupt Source
Receive Data (HRDF = 1)
MOTOROLA
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